Table of Contents

• An experimental MOS fault simulation program CSASIMMasato Kawai, John P. Hayes. 2-9 [doi]
• The second generation motis mixed-mode simulatorChin-Fu Chen, Chi-Yuan Lo, Hao N. Nham, Prasad Subramaniam. 10-17 [doi]
• STAFAN: An alternative to fault simulationSunil K. Jain, Vishwani D. Agrawal. 18-23 [doi]
• THEMIS logic simulator - a mix mode, multi-level, hierarchical, interactive digital circuit simulatorMahesh H. Doshi, Roderick B. Sullivan, Donald M. Schuler. 24-31 [doi]
• A wire routing scheme for double-layer cell arraysGuy Dupenloup. 32-37 [doi]
• An efficient channel routerTakeshi Yoshimura. 38-44 [doi]
• A global routing algorithm for general cellsGary W. Clow. 45-51 [doi]
• A symbolic-interconnect router for custom IC designCharles H. Ng. 52-58 [doi]
• HARPA: A hierarchical multi-level hardware description languagePedro Veiga, Mário Lança. 59-65 [doi]
• ADL: An algorithmic design language for integrated circuit synthesisW. H. Evans, Jean-Claude Ballegeer, Nguyen H. Duyet. 66-72 [doi]
• A symbolic functional description languageGotaro Odawara, Jun Sato, Masahiro Tomita. 73-80 [doi]
• Block description language (BDL): A structural description languageEric Slutz, Glen Okita, Jeanne Wiseman. 81-85 [doi]
• Silicon compilers and expert systems for VLSIDaniel D. Gajski. 86-87 [doi]
• Workshop introduction to gate array placement and routing packagesFrederick Hinchliffe II, R. V. Alessi, J. Bunik, P. Catapano, M. Kubota, R. H. Dean, E. Dorsey, M. Leddell. 89 [doi]
• A technology independent MOS multiplier generatorKung-Chao Chu, Ramautar Sharma. 90-97 [doi]
• The icewater language and interpreterPatrick A. D. Powell, Mohamed I. Elmasry. 98-102 [doi]
• Cell compilation with constraintsChidchanok Lursinsap, Daniel Gajski. 103-108 [doi]
• Efficient implementation of experimental design systemsGeorge D. M. Ross. 109 [doi]
• Extending the relational database data model for design applicationsMartin Hardwick. 110-116 [doi]
• The structure and operation of a relational database system in a cell-oriented integrated circuit design systemLee A. Hollaar, Brent E. Nelson, Tony M. Carter, Raymond A. Lorie. 117-125 [doi]
• A hiererachical, error-tolerant compactorChristopher Kingsley. 126-132 [doi]
• Chip layout optimization using critical path weightingAlfred E. Dunlop, Vishwani D. Agrawal, David N. Deutsch, M. F. Jukl, Patrick Kozak, Manfred Wiesel. 133-136 [doi]
• Interactive compaction router for VLSI layoutHajimu Mori. 137-143 [doi]
• Computer aided design (CAD) using logic programmingPaul W. Horstmann, Edward P. Stabler. 144-151 [doi]
• Magic: A VLSI layout systemJohn K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, George S. Taylor. 152-159 [doi]
• Magic's incremental design-rule checkerGeorge S. Taylor, John K. Ousterhout. 160-165 [doi]
• Plowing: Interactive stretching and compaction in magicWalter S. Scott, John K. Ousterhout. 166-172 [doi]
• A switchbox router with obstacle avoidanceGordon T. Hamachi, John K. Ousterhout. 173-179 [doi]
• Test generation for LSI: A case studyMagdy S. Abadir, Hassan K. Reghbati. 180-195 [doi]
• An approach to the testing of microprocessorsMark G. Karpovsky, Rodney Van Meter. 196-202 [doi]
• Chip partitioning aid: A design technique for partitionability and testability in VLSISubrata Dasgupta, M. C. Graf, Robert A. Rasmussen, Ron G. Walther, Tom W. Williams. 203-208 [doi]
• An integrated design for testability and automatic test pattern generation system: An overviewErwin Trischler. 209-215 [doi]
• Introduction to the SRC design sciences programRalph K. Cavin III. 216-217 [doi]
• Basic turorial layout tools - what really is thereR. Smith. 219 [doi]
• Ergonomic studies in computer aided designGerard H. van der Heiden, Etienne Grandjean. 220-227 [doi]
• Functional verification of memory circuits from mask artwork dataMasahiko Kawamura, Haruo Takagi, Kanji Hirabayashi. 228-234 [doi]
• The scan line approach to design rules checking: Computational experiencesP. T. Chapman, K. Clark Jr.. 235-241 [doi]
• A systolic design rule checkerRajiv Kane, Sartaj Sahni. 243-250 [doi]
• A model for hardware description and verificationGeorge J. Milne. 251-257 [doi]
• A model for non interpreted structures of logical systemsR. Alali, C. Durante, J. J. Mercier. 258-264 [doi]
• Towards a standard hardware description languageKarl J. Lieberherr. 265-272 [doi]
• IGES as an interchange format for integrated circuit designCurtis H. Parks. 273-274 [doi]
• A designing system for multi-family housingBarry Jackson. 275-281 [doi]
• Module design verification systemLloyd Wilkins. 282-287 [doi]
• Studying the mouse for CAD systemsLynne A. Price. 288-293 [doi]
• Amoeba: A symbolic VLSI layout systemMikhail Lotvin, Belinda Juran, Reeni Goldin. 294-300 [doi]
• ARIES: A workstation based, schematic driven system for circuit designWilliam H. Kao, Mohammad H. Movahed-Ezazi, Mark L. Sabiers. 301-307 [doi]
• A high level synthesis tool for MOS chip designJean-Pierre Dussault, Chi-Chang Liaw, Michael M. Tong. 308-314 [doi]
• Emerald: A bus style designerChia-Jeng Tseng, Daniel P. Siewiorek. 315-321 [doi]
• Polaris: Polarity propagation algorithm for combinational logic synthesisT. Shinsha, T. Kubo, M. Hikosaka, K. Akiyama, Koichiro Ishihara. 322-328 [doi]
• A general methodology for synthesis and verification of register-transfer designsAlice C. Parker, Fadi J. Kurdahi, Mitch J. Mlinar. 329-335 [doi]
• Ultimate: A hardware logic simulation engineM. E. Glazier, Anthony P. Ambler. 336-342 [doi]
• Oracle - a simulator for Bipolar and MOS IC designManuel A. d'Abreu, K. L. Cheong, C. T. Flanagan. 343-349 [doi]
• A multiprocessor implementation of relaxation-based electrical circuit simulationJeffrey T. Deutsch, A. Richard Newton. 350-357 [doi]
• Micro-computer oriented algorithms for delay evaluation of MOS gatesDaniel Etiemble, V. Adeline, Nguyen H. Duyet, J. C. Ballegeer. 358-364 [doi]
• A unified CAD system for electronic designJohn C. Foster. 365-369 [doi]
• Engineering design aspectsHerbert Y. Chang, Richard N. Talmadge. 370-373 [doi]
• Physical design and manufacturing information aspects aspects of the AT & T bell laboratories CAD systemCharles W. Rosenthal. 374-383 [doi]
• Users viewJohn Colton, Frank E. Swiatek, D. H. Edwards. 384 [doi]
• Workshop the semi-custom revolution: How to thrive or surviveA. Zingale, F. Kohn, F. Lynch, D. Kalbarsh. 385 [doi]
• Commercial gate array physical design automation packagesFrederick Hinchliffe II. 386-387 [doi]
• The channel expansion problem in layout designRachel R. Chen, Yoji Kajitani. 388-391 [doi]
• A standard cell initial placement strategyBill D. Richard. 392-398 [doi]
• Performance of algorithms for initial placementMichael Palczewski. 399-404 [doi]
• The rectangle placement languageJohn Alan Roach. 405-411 [doi]
• A knowledge based approach to VLSI CAD the redesign systemLouis I. Steinberg, Tom M. Mitchell. 412-418 [doi]
• The CRITTER system: Automated critiquing of digital circuit designsVan E. Kelly. 419-425 [doi]
• A branch and bound algorithm for optimal pla foldingJ. L. Lewandowski, Chang L. Liu. 426-433 [doi]
• A VLSI FSM design systemM. J. Meyer, Prathima Agrawal, R. G. Pfister. 434-440 [doi]
• The semi-automatic generation of processing element control paths for highly parallel machinesTheodore Sabety, David Elliot Shaw, Brian Mathies. 441-446 [doi]
• Managing a large volume of design/manufacturing/test data in a chip and module factoryVincent J. Freund Jr.. 447-451 [doi]
• MINUPROX - an advanced proximity correction technique for the IBM EL-2 electron beam toolW. J. Guillaume, A. Kurylo. 452-453 [doi]
• An automated system for testing LSI memory chipsH. D. Schnurmann, L. J. Vidunas, R. M. Peters. 454-458 [doi]
• The Intel design automation systemStephen Nachtsheim. 459-465 [doi]
• The engineering design environmentKirk Sherhart, Mark Vershel, Judy Owen. 466-472 [doi]
• Functional design verification by multi-level simulationKit Tham, Rob Willoner, David Wimp. 473-478 [doi]
• Performance verification of circuitsJerry Mar, You-Pang Wei. 479-483 [doi]
• Hierarchical layout verificationTodd J. Wagner. 484-489 [doi]
• Taking into account asynchronous signals in functional test of complex circuitsCatherine Bellon, Raoul Velazco. 490-496 [doi]
• VLSI test expertise system using a control flow modelGabriele Saucier, Catherine Bellon. 497-503 [doi]
• A gate level model for CMOS combinational logic circuits with application to fault detectionSudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain. 504-509 [doi]
• Parameterized random testingKarl J. Lieberherr. 510-516 [doi]
• Functional testing techniques for digital LSI/VLSI systemsStephen Y. H. Su, Tonysheng Lin. 517-528 [doi]
• Delay and power optimization in VLSI circuitsLance A. Glasser, Lennox Hoyte. 529-535 [doi]
• IDA: Interconnect delay analysis for integrated circuitsAart J. de Geus, J. B. Reed, M. Rekhson, G. Wikle. 536-541 [doi]
• Switch-level delay models for digital MOS VLSIJohn K. Ousterhout. 542-548 [doi]
• An MOS digital network model on a modified thevenin equivalent for logic simulationTsuyoshi Takahashi, Satoshi Kojima, Osamu Yamashiro, Kazuhiko Eguchi, Hideki Fukuda. 549-555 [doi]
• The VHSIC hardware description language (VHDL) programAl Dewey. 556-557 [doi]
• Phled45: An enhanced version of caesar supporting 45° geometriesAnn R. Lanfri. 558-564 [doi]
• MGX: An integrated symbolic layout system for VLSIMasaru Ozaki, Miho Watanabe, Morio Kakinuma, Mikio Ikeda, Koji Sato. 572-579 [doi]
• UTMC's LSI CAD system - highlandK. Anderson, R. Powell. 580-586 [doi]
• The mimola design system: Tools for the design of digital processorsPeter Marwedel. 587-593 [doi]
• A declarative design approach for combining macrocells by directed placement and constructive routingC. L. Wardle, Charles R. Watson, C. A. Wilson, J. Craig Mudge, Bradley J. Nelson. 594-601 [doi]
• A model for university, industry and government cooperationLawrence Snyder. 602-603 [doi]
• Tutorial - mechanical workstation software computer aided engineering in the mechanical design processJ. Scott. 605 [doi]
• Computervision's direction in workstation technologyGuy D. Haas. 606-609 [doi]
• A technology independent block extraction algorithmF. Luellau, T. Hoepken, Erich Barke. 610-615 [doi]
• EXCL: A circuit extractor for IC designsSteven Paul McCormick. 616-623 [doi]
• An interactive electrical graph extractorJ. L. Kors, M. Israel. 624-628 [doi]
• Some consideration on the data model of geometric data basesJinglun Zhang, Renhua Wang. 629-633 [doi]
• An architecture for application of artificial intelligence to designJohn R. Dixon, Melvin K. Simmons, Paul R. Cohen. 634-640 [doi]
• A formal design verification system based on an automated reasoning systemAnthony S. Wojcik, Joseph Kljaich Jr., Nagendra C. E. Srinivas. 641-647 [doi]
• Hardware accelerators in the design automation environmentRam Banin. 648 [doi]
• The semi-custom revolution: How to thrive or surviveAnthony Zingale. 649-650 [doi]
• Optimization techniques for two-dimensional placementLev A. Markov, Jeffrey R. Fox, John H. Blank. 652-654 [doi]
• An algorithm for finding a rectangular dual of a planar graph for use in area planning for VLSI integrated circuitsKrzysztof Kozminski, Edwin Kinnen. 655-656 [doi]
• GALA - an automatic layout system for high density CMOS gate arraysBou Nin Tien, B. S. Ting, J. Cheam, Kenneth S. K. Chow, Scott C. Evans. 657-662 [doi]
• An algorithm for building rectangular floor-plansSany M. Leinwand, Yen-Tai Lai. 663-664 [doi]
• Spider, a chip planner for ISL technologyPrakash Rao, R. Ramnarayan, Gerhard Zimmermann. 665-666 [doi]
• Combine and top down block placement algorithm for hierarchical logic VLSI layoutTokinori Kozawa, Chihei Miura, Hidekazu Terai. 667-669 [doi]
• Initial placement of gate arrays using least-squares methodsJohn P. Blanks. 670-671 [doi]
• Module positioning algorithms for rectilinear macrocell assembliesJack A. Hudson, John A. Wisniewski, Randy C. Peters. 672-675 [doi]
• Microprocessor synthesisVijay K. Raj, Barry M. Pangrle, Daniel D. Gajski. 676-678 [doi]
• Topological routing of multi-bit data busesG. Persky, L. V. Tran. 679-682 [doi]
• An electronic design interchange formatJohn D. Crawford. 683-685 [doi]
• A VLSI design methodology based on parametric macro cellsR. A. Kriete, R. K. Nettleton. 686-688 [doi]
• Methodology for compiler generated silicon structuresAntonio Martínez, Scott Nance. 689-691 [doi]
• Design transaction managementRandy H. Katz, Shlomo Weiss. 692-693 [doi]
• Uniform support for information handling and problem solving required by the VLSI design processV. Ashok, Walter Lee McKnight, Jayashree Ramanathan. 694-696 [doi]
• VTIcompose - a powerful graphical chip assembly toolStephen Trimberger. 697-698 [doi]
• Computer aided minimization procedure for boolean functionsNripendra N. Biswas. 699-702 [doi]
• Optimization of negative gate networks realized in weinberger-LIKF layout in a boolean level silicon compilerAndrzej Wieclawski, Marek A. Perkowski. 703-704 [doi]
• Deadlock analysis in the design of data-flow circuitsChu S. Jhon, Robert M. Keller. 705-707 [doi]
• A method for IC layout verificationOla A. Marvik. 708-709 [doi]
• On the relation between wire length distributions and placement of logic on master slice ICsSarma Sastry, Alice C. Parker. 710-711 [doi]