Nripendra N. Biswas - researchr alias

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Viewing Publication 1 - 29 from 29

1996

Cubical CAMP for minimization of Boolean functionsNripendra N. Biswas, C. Srikanth, James Jacob. vlsid 1996: 264-269 [doi]

1993

Logic design theoryNripendra N. Biswas. Prentice Hall, 1993.

1992

Design and Analysis of a Generalized Architecture for Reconfigurable m-ary Tree StructuresSampalli Srinivas, Nripendra N. Biswas. TC, 41(11):1465-1478, 1992.

1990

A Reconfigurable Tree Architecture with Multistage Interconnection NetworkNripendra N. Biswas, Sampalli Srinivas. TC, 39(12):1481-1485, 1990.

On covering distant minterms by the camp algorithmNripendra N. Biswas. tcad, 9(7):786-789, 1990. [doi]

Further Comments on Detection of Faults in Programmable Logic Arrays James Jacob, Nripendra N. Biswas. TC, 39(1):155-157, 1990.

1989

An algorithm for multiple output minimizationB. Gurunath, Nripendra N. Biswas. tcad, 8(9):1007-1013, 1989. [doi]

1988

Design of Crosspoint-Irredundant PLA s Using Minimal Number of Control InputsK. S. Ramanatha, Nripendra N. Biswas. TC, 37(9):1130-1134, 1988.

1987

A centrally controlled shuffle network for reconfigurable and fault-tolerant architectureNripendra N. Biswas, Sampalli Srinivas, Trishala Dharanendra. sigarch, 15(1):81-87, 1987. [doi]

Simple methods for the calculation of root of a reconfigurable binary tree structureNripendra N. Biswas, S. Srinivas. pieee, 75(12):1690-1692, 1987. [doi]

1986

Computer-Aided Minimization Procedure for Boolean FunctionsNripendra N. Biswas. tcad, 5(2):303-304, 1986. [doi]

1985

Multiple output minimizationPrathima Agrawal, Vishwani D. Agrawal, Nripendra N. Biswas. dac 1985: 674-680 [doi]

On Bit Steering in the Minimization of the Control Memory of Microprogrammed ProcessorsNripendra N. Biswas. TC, 34(11):1057-1061, 1985.

: A Testable PLA Design with Minimal Hardware and Test SetJames Jacob, Nripendra N. Biswas. itc 1985: 583-588

1984

Computer aided minimization procedure for boolean functionsNripendra N. Biswas. dac 1984: 699-702 [doi]

1983

An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic ArraysK. S. Ramanatha, Nripendra N. Biswas. TC, 32(5):438-444, 1983.

A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic ArraysK. S. Ramanatha, Nripendra N. Biswas. TC, 32(6):551-557, 1983.

On the Minimization of Wordwidth in the Control Memory of a Microprogrammed Digital ComputerChamarty D. V. P. Rao, Nripendra N. Biswas. TC, 32(9):863-868, 1983.

1982

A Design for Complete Testability of Programmable Logic ArraysK. S. Ramanatha, Nripendra N. Biswas. itc 1982: 67-74

1981

Bit Steering in the Minimization of Control Memory in Microprogrammed Digital ComputersAyakannu Mathialagan, Nripendra N. Biswas. TC, 30(2):144-147, 1981.

1980

Optimal Interconnections in the Design of Microprocessors and Digital SystemsAyakannu Mathialagan, Nripendra N. Biswas. TC, 29(2):145-149, 1980.

1979

A New Approach to 2-Asummability TestingAnil K. Sarje, Nripendra N. Biswas. TC, 28(10):798-801, 1979.

1977

An Algorithm for Testing 2-Asummability of Boolean FunctionsAnil K. Sarje, Nripendra N. Biswas. TC, 26(10):1049-1053, 1977.

1976

Further Comments on Closure Partition Method for Minimizing Incomplete Sequential MachinesC. V. S. Rao, Nripendra N. Biswas. TC, 25(7):767-768, 1976.

1975

Minimization of Incompletely Specified Sequential MachinesC. V. S. Rao, Nripendra N. Biswas. TC, 24(11):1089-1100, 1975.

1974

State Minimization of Incompletely Specified Sequential MachinesNripendra N. Biswas. TC, 23(1):80-84, 1974. [doi]

1973

Comments on "Identification of Totally Symmetric Boolean Functions"Nripendra N. Biswas. TC, 22(9):863-864, 1973. [doi]

1971

Minimization of Boolean FunctionsNripendra N. Biswas. TC, 20(8):925-929, 1971. [doi]

1970

On Identification of Totally Symmetric Boolean FunctionsNripendra N. Biswas. TC, 19(7):645-648, 1970. [doi]

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