Abstract is missing.
- Efficient scheduling of fine grain parallelism in loopsM. Rajagopalan, Vicki H. Allan. 2-11 [doi]
- Employing finite automata for resource schedulingThomas Müller. 12-20 [doi]
- GPMB - software pipelining branch-intensive loopsZhizhong Tang, Gang Chen, Chihong Zhang, Yingwei Zhang, Bogong Su, Stanley Habib. 21-30 [doi]
- A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor busTimothy J. Stanley, Michael Upton, Patrick Sherhart, Trevor N. Mudge, Richard B. Brown. 31-40 [doi]
- Two-ported cache alternatives for superscalar processorsAndrew Wolfe, Rodney Boleyn. 41-48 [doi]
- A study on the number of memory ports in multiple instruction issue machinesSoo-Mook Moon, Kemal Ebcioglu. 49-59 [doi]
- The 16-fold way: a microparallel taxonomyBarton Sano, Alvin M. Despain. 60-69 [doi]
- A comparative performance evaluation of various state maintenance mechanismsMichael Butler, Yale N. Patt. 70-79 [doi]
- Dynamically scheduled VLIW processorsB. Ramakrishna Rau. 80-92 [doi]
- Prophetic branches: a branch architecture for code compaction and efficient executionApoorv Srivastava, Alvin M. Despain. 94-99 [doi]
- A comparision of superscalar and decoupled access/execute architecturesMatthew K. Farrens, Pius Ng, Phil Nico. 100-103 [doi]
- Measuring limits of parallelism and characterizing its vulnerability to resource constraintsLawrence Rauchwerger, Pradeep K. Dubey, Ravi Nair. 105-117 [doi]
- An evaluation of bottom-up and top-down thread generation techniquesA. P. Wim Böhm, Walid A. Najjar, Bhanu Shankar, Lucas Roh. 118-127 [doi]
- Techniques for extracting instruction level parallelism on MIMD architecturesGary S. Tyson, Matthew K. Farrens. 128-137 [doi]
- Predictability of load/store instruction latenciesSantosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. Ramakrishna Rau, Rajiv Gupta. 139-152 [doi]
- Control flow prediction for dynamic ILP processorsDionisios N. Pnevmatikatos, Manoj Franklin, Gurindar S. Sohi. 153-163 [doi]
- Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processorsTse-Yu Yeh, Yale N. Patt. 164-175 [doi]
- Clocked and asynchronous instruction pipelinesMark A. Franklin, Tienyo Pan. 177-184 [doi]
- An analysis of dynamic scheduling techniques for symbolic applicationsAlessandra Costa, Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri. 185-191 [doi]
- MIDEE: smoothing branch and instruction cache miss penalties on deep pipelinesNathalie Drach, André Seznec. 193-201 [doi]
- Register renaming and dynamic speculation: an alternative approachMayan Moudgill, Keshav Pingali, Stamatis Vassiliadis. 202-213 [doi]
- Speculative execution exception recovery using write-back suppressionRoger A. Bringmann, Scott A. Mahlke, Richard E. Hank, John C. Gyllenhaal, Wen-mei W. Hwu. 214-223 [doi]
- EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processorsTrung A. Diep, John Paul Shen, Mike Phillip. 225-235 [doi]
- An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processorsIng-Jer Huang, Alvin M. Despain. 236-246 [doi]
- Superblock formation using static program analysisRichard E. Hank, Scott A. Mahlke, Roger A. Bringmann, John C. Gyllenhaal, Wen-mei W. Hwu. 247-255 [doi]
- Instruction scheduling for the Motorola 88110Mark Smotherman, Shuchi Chawla II, Stan Cox, Brian A. Malloy. 257-262 [doi]
- A VLIW architecture based on shifting register filesH. Fatih Ugurdag, Christos A. Papachristou. 263-268 [doi]