Table of Contents

• A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC-IMarc Tremblay, Guillermo Maturana, Atsushi Inoue, Leslie Kohn. 2-6 [doi]
• System Design Methodology of UltraSPARC-ILawrence Yang, David Gao, Jamshid Mostoufi, Raju Joshi, Paul Loewenstein. 7-12 [doi]
• UltraSPARC-I EmulationJames Gateley, Miriam Blatt, Dennis Chen, Scott Cooke, Piyush Desai, Manjunath Doreswamy, Mark Elgood, Gary Feierbach, Tim Goldsbury, Dale Greenley, Raju Joshi, Mike Khosraviani, Robert Kwong, Manish Motwani, Chitresh Narasimhaiah, Sam J. Nicolino Jr., Tooru Ozeki, Gary Peterson, Chris Salzmann, Nasser Shayesteh, Jeffrey Whitman, Pak Wong. 13-18 [doi]
• CAD Methodology for the Design of UltraSPARC-I Microprocessor at Sun Microsystems IncA. Cao, A. Adalal, J. Bauman, P. Delisle, P. Dedood, P. Donehue, M. Dell OcaKhouja, T. Doan, Manjunath Doreswamy, P. Ferolito, O. Geva, D. Greenhill, S. Gopaladhine, J. Irwin, L. Lev, J. MacDonald, M. Ma, Samir Mitra, P. Patel, A. Prabhu, R. Puranik, S. Rozanski, N. Ross, P. Saggurti, S. Simovich, R. Sunder, B. Sur, W. Vercruysse, Michelle Wong, P. Yip, Robert K. Yu, J. Zhou, Gregory B. Zyner. 19-22 [doi]
• Computing the Maximum Power Cycles of a Sequential CircuitSrilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino. 23-28 [doi]
• Register Allocation and Binding for Low PowerJui-Ming Chang, Massoud Pedram. 29-35 [doi]
• Memory Segmentation to Exploit Sleep Mode OperationAmir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh. 36-41 [doi]
• Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral LevelRaul San Martin, John P. Knight. 42-47 [doi]
• Boolean Matching for Incompletely Specified FunctionsKuo-Hua Wang, TingTing Hwang. 48-53 [doi]
• Functional Multiple-Output Decomposition: Theory and an Implicit AlgorithmBernd Wurth, Klaus Eckl, Kurt Antreich. 54-59 [doi]
• A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA SynthesisTed Stanion, Carl Sechen. 60-64 [doi]
• Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology MappingWen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao. 65-69 [doi]
• Minimizing the Routing Cost During Logic ExtractionHirendu Vaishnav, Massoud Pedram. 70-75 [doi]
• Requirements-Based Design EvaluationStephen T. Frezza, Steven P. Levitan, Panos K. Chrysanthis. 76-81 [doi]
• Incorporating Design Schedule Management into a Flow Management SystemEric W. Johnson, Jay B. Brockman. 82-87 [doi]
• Tool Integration and Construction Using Generated Graph-Based Design RepresentationsAnsgar Bredenfeld, Raul Camposano. 94-99 [doi]
• Scheduling Using Behavioral TemplatesTai Ly, David Knapp, Ron Miller, Don MacMillen. 101-106 [doi]
• Rephasing: A Transformation Technique for the Manipulation of Timing ConstraintsMiodrag Potkonjak, Mani B. Srivastava. 107-112 [doi]
• Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and RetimingY. G. DeCastelo-Vide-e-Souza, Miodrag Potkonjak, Alice C. Parker. 113-118 [doi]
• Fast Identification of Robust Dependent Path Delay FaultsUwe Sparmann, D. Luxenburger, Kwang-Ting Cheng, Sudhakar M. Reddy. 119-125 [doi]
• On Synthesis-for-Testability of Combinational Logic CircuitsIrith Pomeranz, Sudhakar M. Reddy. 126-132 [doi]
• Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact ListsSrikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel. 133-138 [doi]
• Parallel Logic Simulation of VLSI SystemsRoger D. Chamberlain. 139-143 [doi]
• A General Method for Compiling Event-Driven SimulationsRobert S. French, Monica S. Lam, Jeremy R. Levitt, Kunle Olukotun. 151-156 [doi]
• A Transformation-Based Approach for Storage OptimizationWei-Kai Cheng, Youn-Long Lin. 158-163 [doi]
• Register Minimization beyond Sharing among VariablesTsung-Yi Wu, Youn-Long Lin. 164-169 [doi]
• Constrained Register Allocation in Bus ArchitecturesElof Frank, Salil Raje, Majid Sarrafzadeh. 170-175 [doi]
• On Test Set Preservation of Retimed CircuitsAiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly. 176-182 [doi]
• Partial Scan with Pre-selected Scan SignalsPeichen Pan, C. L. Liu. 189-194 [doi]
• Spectral Partitioning: The More Eigenvectors, The BetterCharles J. Alpert, So-Zen Yao. 195-200 [doi]
• Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAsPrashant Sawkar, Donald E. Thomas. 201-205 [doi]
• Performance-Driven Partitioning Using a Replication Graph ApproachLung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu. 206-210
• Timing Driven Placement for Large Standard Cell CircuitsWilliam Swartz, Carl Sechen. 211-215 [doi]
• Quantified Suboptimality of VLSI Layout HeuristicsLars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng. 216-221 [doi]
• Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD - CCS7E Processor System SimulationThomas W. Albrecht. 222-227 [doi]
• Digital Receiver Design Using VHDL Generation from Data Flow GraphsPeter Zepter, Thorsten Grötker, Heinrich Meyr. 228-233 [doi]
• A Survey of Optimization Techniques Targeting Low Power VLSI CircuitsSrinivas Devadas, Sharad Malik. 242-247 [doi]
• Logic Extraction and Factorization for Low PowerSasan Iman, Massoud Pedram. 248-253 [doi]
• Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis ToolLuciano Lavagno, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli. 254-260 [doi]
• The Aurora RAM CompilerAjay Chandna, C. David Kibler, Richard B. Brown, Mark Roberts, Karem A. Sakallah. 261-266 [doi]
• Automatic Layout Synthesis of Leaf CellsSanjay Rekhi, J. Donald Trotter, Daniel H. Linder. 267-272 [doi]
• Delayed Frontal Solution for Finite-Element Based Resistance ExtractionN. P. van der Meijs, Arjan J. van Genderen. 273-278 [doi]
• Behavioral Synthesis Methodology for HDL-Based Specification and ValidationDavid Knapp, Tai Ly, Don MacMillen, Ron Miller. 286-291 [doi]
• Design-Flow and Synthesis for ASICs: A Case StudyMassimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Roger B. Hughes, Gerry Musgrave, Giuseppe Zaza. 292-297 [doi]
• Model Checking in Industrial Hardware DesignJörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl. 298-303 [doi]
• DELAY: An Efficient Tool for Retiming with Realistic Delay ModelingKumar N. Lalgudi, Marios C. Papaefthymiou. 304-309 [doi]
• A Fresh Look at Retiming Via Clock Skew OptimizationRahul B. Deokar, Sachin S. Sapatnekar. 310-315 [doi]
• The Validity of Retiming Sequential CircuitsVigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton. 316-321 [doi]
• Retiming Synchronous Circuitry with Imprecise DelaysIreneusz Karkowski, Ralph H. J. M. Otten. 322-326 [doi]
• A Fast State Assignment Procedure for Large FSMsShihming Liu, Massoud Pedram, Alvin M. Despain. 327-332 [doi]
• Software Accelerated Functional Fault Simulation for Data-Path ArchitecturesMark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. 333-338 [doi]
• Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test StrategyRolf Krieger, Bernd Becker, Martin Keim. 339-344 [doi]
• Accurate and Efficient Fault Simulation of Realistic CMOS Network BreaksHaluk Konuk, F. Joel Ferguson, Tracy Larrabee. 345-351 [doi]
• Analysis of Switch-Level Faults by Symbolic SimulationLluis Ribas, Jordi Carrabina. 352-357 [doi]
• Transmission Line SynthesisByron Krauter, Rohini Gupta, John Willis, Lawrence T. Pileggi. 358-363 [doi]
• The Elmore Delay as a Bound for RC Trees with Generalized Input SignalsRohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi. 364-369 [doi]
• Delay Analysis of the Distributed RC LineVasant B. Rao. 370-375 [doi]
• Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect StructuresLuis Miguel Silveira, Mattan Kamon, Jacob White. 376-380 [doi]
• Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMsSharad Mehrotra, Paul D. Franzon, Michael Steer. 381-387 [doi]
• Symbolic Modeling and Evaluation of Data PathsChuck Monahan, Forrest Brewer. 389-394 [doi]
• Data Path Allocation for Synthesizing RTL Designs with Low BIST Area OverheadIshwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer. 395-401 [doi]
• Deriving Efficient Area and Delay Estimates by Modeling Layout ToolsDonald S. Gelosh, Dorothy E. Setliff. 402-407 [doi]
• Efficient OBDD-Based Boolean Manipulation in CAD beyond Current LimitsJochen Bern, Christoph Meinel, Anna Slobodová. 408-413 [doi]
• Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis EnvironmentSubodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan. 414-419
• Advanced Verification Techniques Based on LearningJawahar Jain, Rajarshi Mukherjee, Masahiro Fujita. 420-426 [doi]
• Efficient Generation of Counterexamples and Witnesses in Symbolic Model CheckingEdmund M. Clarke, Orna Grumberg, Kenneth L. McMillan, Xudong Zhao. 427-432 [doi]
• Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate MacromodelsIvan L. Wemple, Andrew T. Yang. 439-444 [doi]
• Direct Performance-Driven Placement of Mismatch-Sensitive Analog CircuitsKoen Lampaert, Georges G. E. Gielen, Willy M. C. Sansen. 445-449 [doi]
• System-Level Design for Test of Fully Differential Analog CircuitsBapiraju Vinnakota, Ramesh Harjani, Nicholas J. Stessman. 450-454 [doi]
• Performance Analysis of Embedded Software Using Implicit Path EnumerationYau-Tsun Steven Li, Sharad Malik. 456-461 [doi]
• Interval Scheduling: Fine-Grained Code Scheduling for Embedded SystemsPai H. Chou, Gaetano Borriello. 462-467 [doi]
• Interfacing Incompatible Protocols Using Interface Process GenerationSanjiv Narayan, Daniel Gajski. 468-473 [doi]
• Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos AlgorithmPeter Feldmann, Roland W. Freund. 474-479 [doi]
• Efficient Steady-State Analysis Based on Matrix-Free Krylov-Subspace MethodsRicardo Telichevesky, Kenneth S. Kundert, Jacob White. 480-484 [doi]
• Transient Simulations of Three-Dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume ApproachMike Chou, Tom Korsmeyer, Jacob White. 485-490 [doi]
• Power Optimal Buffered Clock Tree DesignAshok Vittal, Malgorzata Marek-Sadowska. 497-502 [doi]
• Power Distribution Topology DesignAshok Vittal, Malgorzata Marek-Sadowska. 503-507 [doi]
• On the Bounded-Skew Clock and Steiner Routing ProblemsDennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Albert Tsao. 508-513 [doi]
• Benchmarking An Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical SystemsAsim Smailagic, Daniel P. Siewiorek, Drew Anderson, Chris Kasabach, Thomas L. Martin, John Stivoric. 514-519 [doi]
• A Methodology for HW-SW Codesign in ATMGiovanni Mancini, Dave Yurach, Spiros Boucouris. 520-527 [doi]
• Accelerating Concurrent Hardware Design with Behavioural Modelling and System SimulationAllan Silburt, Ian Perryman, Janick Bergeron, Stacy Nichols, Mario Dufresne, Greg Ward. 528-533 [doi]
• Verification of Arithmetic Circuits with Binary Moment DiagramsRandal E. Bryant, Yirng-An Chen. 535-541 [doi]
• Residue BDD and Its Application to the Verification of Arithmetic CircuitsShinji Kimura. 542-545 [doi]
• Equivalence Checking of Datapaths Based on Canonical Arithmetic ExpressionsZheng Zhou, Wayne Burleson. 546-551 [doi]
• On Optimal Board-Level Routing for FPGA-Based Logic EmulationWai-Kei Mak, D. F. Wong. 552-556 [doi]
• A Performance and Routability Driven Router for FPGAs Considering Path DelaysYuh-Sheng Lee, Allen C.-H. Wu. 557-561 [doi]
• New Performance-Driven FPGA Routing AlgorithmsMichael J. Alexander, Gabriel Robins. 562-567 [doi]
• Effects of FPGA Architecture on FPGA RoutingSteven Trimberger. 574-578 [doi]
• The Case for Design Using the World Wide WebMário J. Silva, Randy H. Katz. 579-585 [doi]
• Synthesis of Software Programs for Embedded Control ApplicationsMassimiliano Chiodo, Paolo Giusto, Attila Jurecska, Luciano Lavagno, Harry Hsieh, Kei Suzuki, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich. 587-592 [doi]
• Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP CoresAdwin H. Timmer, Marino T. J. Strik, Jef L. van Meerbergen, Jochen A. G. Jess. 593-598 [doi]
• Code Optimization Techniques for Embedded DSP Microprocessors599-604 [doi]
• Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI CircuitsFarid N. Najm. 612-617 [doi]
• Accurate Estimation of Combinational Circuit ActivityHuzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin. 618-622 [doi]
• Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI CircuitsFarid N. Najm, Michael Y. Zhang. 623-627 [doi]
• Efficient Power Estimation for Highly Correlated Input StreamsRadu Marculescu, Diana Marculescu, Massoud Pedram. 628-634 [doi]
• Power Estimation in Sequential CircuitsFarid N. Najm, Shashank Goel, Ibrahim N. Hajj. 635-640 [doi]
• New Ideas for Solving Covering ProblemsOlivier Coudert, Jean Christophe Madre. 641-646 [doi]
• Logic Synthesis for Engineering ChangeChih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng. 647-652 [doi]
• A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean MatrixYuichi Nakamura, Takeshi Yoshimura. 653-657 [doi]
• Multi-Level Logic Minimization Based on Multi-Signal ImplicationsMasayuki Yuguchi, Yuichi Nakamura, Kazutoshi Wakabayashi, Tomoyuki Fujita. 658-662 [doi]
• An Efficient Algorithm for Local Don t Care Sets CalculationShih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng. 663-667 [doi]
• Logic Clause Analysis for Delay OptimizationBernhard Rohfleisch, Bernd Wurth, Kurt Antreich. 668-672 [doi]
• Productivity Issues in High-Level Design: Are Tools Solving the Real Problems?Reinaldo A. Bergamaschi. 674-677 [doi]
• Information Models of VHDLCristian A. Giumale, Hilary J. Kahn. 678-683 [doi]
• Measures of Syntactic Complexity for Modeling Behavioral VHDLNeal S. Stollon, John D. Provence. 684-689 [doi]
• Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay OptimizationNoel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi. 690-695 [doi]
• An Algorithm for Incremental Timing AnalysisJin-fuw Lee, Donald T. Tang. 696-701 [doi]
• An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard CellsAlessandro Dal Fabbro, Bruno Franzini, Luigi Croce, Carlo Guardiani. 702-706 [doi]
• Automatic Clock Abstraction from Sequential CircuitsSamir Jain, Randal E. Bryant, Alok Jain. 707-711 [doi]
• Hierarchical Optimization of Asynchronous CircuitsBill Lin, Gjalt G. de Jong, Tilman Kolks. 712-717 [doi]
• Externally Hazard-Free Implementations of Asynchronous CircuitsMilton H. Sawasaki, Chantal Ykman-Couvreur, Bill Lin. 718-724 [doi]
• A Design and Validation System for Asynchronous CircuitsPeter Vanbekbergen, Albert Wang, Kurt Keutzer. 725-730 [doi]