Vasant B. Rao - researchr alias

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2011

2002

Aggressive crunching of extracted RC netlistsVasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang. tau 2002: 70-77 [doi]

1996

Design planning for high-performance ASICsJohn Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit Dasgupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang. ibmrd, 40(4):431-452, 1996. [doi]

1995

Delay Analysis of the Distributed RC LineVasant B. Rao. dac 1995: 370-375 [doi]

1993

Constructive Heuristics and Lower Bounds for Graph Partitioning Based on a Principal-Components ApproximationK. S. Arun, Vasant B. Rao. siammax, 14(4):991-1015, October 1993. [doi]

On the Convergence of Reversible Markov ChainsMadhav P. Desai, Vasant B. Rao. siammax, 14(4):950-966, October 1993. [doi]

An exact solution to the transistor sizing problem for CMOS circuits using convex optimizationSachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang. tcad, 12(11):1621-1634, 1993. [doi]

1991

1990

Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout ProblemsYoussef Saab, Vasant B. Rao. dac 1990: 26-31 [doi]

Fast effective heuristics for the graph bisectioning problemYoussef Saab, Vasant B. Rao. tcad, 9(1):91-98, 1990. [doi]

1989

A Stochastic Algorithm for Circuit Bi-PartitioningYoussef Saab, Vasant B. Rao. glakes 1991: 313-321

An Evolution-Based Approach to Partitioning ASIC SystemsYoussef Saab, Vasant B. Rao. dac 1989: 767-770 [doi]

1988

Multi-Input Fuzzy Inference Engine on a Systolic ArrayM. A. Manzoul, Vasant B. Rao. ieaaie 1988: 958-964 [doi]

Partitioning issues in circuit simulation on multiprocessorsDavid C. Yeh, Vasant B. Rao. iccad 1988: 300-303 [doi]

1987

Network Partitioning and Ordering for MOS VLSI CircuitsVasant B. Rao, Timothy N. Trick. tcad, 6(1):128-144, 1987. [doi]

HPEX: A Hierarchical Parasitic Circuit ExtractorShun-Lin Su, Vasant B. Rao, Timothy N. Trick. dac 1987: 566-569 [doi]

1985

Switch-Level Timing Simulation of MOS VLSI CircuitsVasant B. Rao. PhD thesis, University of Illinois Urbana-Champaign, USA, 1985. [doi]

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