Abstract is missing.
- Explicit computation of performance as a function of process variationLouis Scheffer. 1-8 [doi]
- A probabilistic approach to clock cycle predictionJoni Dambre, Dirk Stroobandt, Jan Van Campenhout. 9-15 [doi]
- Statistical timing analysis using bounds and selective enumerationAseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula. 16-21 [doi]
- Worst case clock skew under power supply variationsMin Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal. 22-28 [doi]
- Statistical timing analysis using bounds and selective enumerationAseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula. 29-36 [doi]
- From blind certainty to informed uncertaintyKurt Keutzer, Michael Orshansky. 37-41 [doi]
- Timing analysis challenges for high speed CPUs at 90nm and belowAvi Efrati, Moshe Kleyner. 42 [doi]
- Minimum-power retiming for dual-supply CMOS circuitsFarhana Sheikh, Andreas Kuehlmann, Kurt Keutzer. 43-49 [doi]
- Efficient algorithms for debugging timing constraint violationsAli Dasdan. 50-56 [doi]
- PERI: a technique for extending delay and slew metrics to ramp inputsChandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan. 57-62 [doi]
- A library compatible driving point model for on-chip RLC interconnectsKanak Agarwal, Dennis Sylvester, David Blaauw. 63-69 [doi]
- Aggressive crunching of extracted RC netlistsVasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang. 70-77 [doi]
- Clock schedule verification with crosstalkHai Zhou. 78-83 [doi]
- Efficient switching window computation for cross-talk noiseBhavana Thudi, David Blaauw. 84-91 [doi]
- Determination of worst-case crosstalk noise for non-switching victims in GHz+ busesJun Chen, Lei He. 92-97 [doi]
- Active shielding of RLC global interconnectsHimanshu Kaul, Dennis Sylvester, David Blaauw. 98-104 [doi]
- Wireless interconnects for clock distributionBrian A. Floyd, Xiaoling Guo, James Caserta, Timothy O. Dickson, Chih-Ming Hung, Kihong Kim, K. O. Kenneth. 105-108 [doi]
- Test structures for delay variabilityDuane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu. 109 [doi]
- Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skewBaris Taskin, Ivan S. Kourtev. 111-118 [doi]
- Quadratic deferred-merge embedding algorithm for zero skew clock distribution networkHaydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili. 119-125 [doi]
- Transistor sizing of energy-delay--efficient circuitsPaul I. Pénzes, Mika Nyström, Alain J. Martin. 126-133 [doi]
- The statistical longest path problem and its application to delay analysis of logical circuitsEi Ando, Masafumi Yamashita, Toshio Nakata, Yusuke Matsunaga. 134-139 [doi]
- Reducing probabilistic timed petri nets for asynchronous architectural analysisSangyun Kim, Sunan Tugsinavisut, Peter A. Beerel. 140-147 [doi]