Gustavo E. Téllez - researchr alias

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Viewing Publication 1 - 20 from 20

2022

LEO: Line End Optimizer for Sub-7nm Technology NodesDiwesh Pandey, Gustavo E. Téllez, James Leland. ispd 2022: 117-125 [doi]

2020

Latch Clustering for Timing-Power Co-OptimizationChau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang. dac 2020: 1-6 [doi]

Self-Aligned Double-Patterning Aware LegalizationHua Xiang, Gi-Joon Nam, Gustavo E. Téllez, Shyam Ramji, Xiaoqing Xu. date 2020: 1145-1150 [doi]

2018

Interconnect Optimization Considering Multiple Critical PathsJiang Hu, Ying Zhou, Yaoguang Wei, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Téllez, Gi-Joon Nam. ispd 2018: 132-138 [doi]

On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning TechniquesAlexey Lvov, Gustavo E. Téllez, Gi-Joon Nam. ispd 2018: 152-159 [doi]

2015

Detailed Routing Algorithms for Advanced Technology NodesMarkus Ahrens, Michael Gester, Niko Klewinghaus, Dirk Müller 0003, Sven Peyer, Christian Schulte 0002, Gustavo E. Téllez. tcad, 34(4):563-576, 2015. [doi]

2014

Techniques for scalable and effective routability evaluationYaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar. todaes, 19(2):17, 2014. [doi]

2012

GLARE: global and local wiring aware routability evaluationYaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar. dac 2012: 768-773 [doi]

2011

2001

Activity-driven clock designAmir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh. tcad, 20(6):705-714, 2001. [doi]

1998

Exploiting Sleep Mode for Memory Partitioning and Other ApplicationsAmir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh. vlsi, 1998(3):271-287, 1998. [doi]

On Rectilinear Distance-Preserving TreesGustavo E. Téllez, Majid Sarrafzadeh. vlsi, 1998(1):15-30, 1998. [doi]

1997

1995

Memory Segmentation to Exploit Sleep Mode OperationAmir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh. dac 1995: 36-41 [doi]

Activity-driven clock design for low power circuitsGustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh. iccad 1995: 62-65 [doi]

On Rectilinear Distance-Preserving TreesGustavo E. Téllez, Majid Sarrafzadeh. iscas 1995: 163-166

1994

Clock period constrained minimal buffer insertion in clock treesGustavo E. Téllez, Majid Sarrafzadeh. iccad 1994: 219-223 [doi]

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