Table of Contents

• Biomedical electronics serving as physical environmental and emotional watchdogsRudy Lauwereins. 1-5 [doi]
• Integrated biosensors for personalized medicineGiovanni De Micheli, Cristina Boero, Camilla Baj-Rossi, Irene Taurino, Sandro Carrara. 6-11 [doi]
• Design challenges for secure implantable medical devicesWayne Burleson, Shane S. Clark, Benjamin Ransford, Kevin Fu. 12-17 [doi]
• Design of pin-constrained general-purpose digital microfluidic biochipsYan Luo, Krishnendu Chakrabarty. 18-25 [doi]
• Path scheduling on digital microfluidic biochipsDaniel Grissom, Philip Brisk. 26-35 [doi]
• Realizing reversible circuits using a new class of quantum gatesZahra Sasanian, Robert Wille, D. Michael Miller. 36-41 [doi]
• Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistorsShashikanth Bobba, Michele De Marchi, Yusuf Leblebici, Giovanni De Micheli. 42-47 [doi]
• A semiempirical model for wakeup time estimation in power-gated logic clustersVivek D. Tovinakere, Olivier Sentieys, Steven Derrien. 48-55 [doi]
• Cost-effective power delivery to support per-core voltage domains for power-constrained processorsHamid Reza Ghasemi, Abhishek A. Sinkar, Michael J. Schulte, Nam Sung Kim. 56-61 [doi]
• A hybrid and adaptive model for predicting register file and SRAM power using a reference designEric Donkoh, Alicia Lowery, Emily Shriver. 62-67 [doi]
• Coding-based energy minimization for phase change memoryAzalia Mirhoseini, Miodrag Potkonjak, Farinaz Koushanfar. 68-76 [doi]
• A code morphing methodology to automate power analysis countermeasuresGiovanni Agosta, Alessandro Barenghi, Gerardo Pelosi. 77-82 [doi]
• Security analysis of logic obfuscationJeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, Ramesh Karri. 83-89 [doi]
• Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitrySheng Wei, Kai Li, Farinaz Koushanfar, Miodrag Potkonjak. 90-95 [doi]
• On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correctionDomenic Forte, Ankur Srivastava. 96-105 [doi]
• Transformer: a functional-driven cycle-accurate multicore simulatorZhenman Fang, Qinghao Min, Keyong Zhou, Yi Lu, Yibin Hu, Weihua Zhang, Haibo Chen, Jian Li, Binyu Zang. 106-114 [doi]
• SAGA: SystemC acceleration on GPU architecturesSara Vinco, Debapriya Chatterjee, Valeria Bertacco, Franco Fummi. 115-120 [doi]
• Synchronization for hybrid MPSoC full-system simulationLuis Gabriel Murillo, Juan Fernando Eusse, Jovana Jovic, Sergey Yakoushkin, Rainer Leupers, Gerd Ascheid. 121-126 [doi]
• A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulationYu-Hung Huang, Yi-Shan Lu, Hsin-I. Wu, Ren-Song Tsay. 127-132 [doi]
• Can EDA combat the rise of electronic counterfeiting?Farinaz Koushanfar, Saverio Fazzari, Carl McCants, William Bryson, Matthew Sale, Peilin Song, Miodrag Potkonjak. 133-138 [doi]
• Physics matters: statistical aging prediction under trapping/detrappingJyothi Bhaskarr Velamala, Ketul Sutaria, Takashi Sato, Yu Cao. 139-144 [doi]
• Library-aware resonant clock synthesis (LARCS)Xuchu Hu, Walter James Condley, Matthew R. Guthaus. 145-150 [doi]
• Incremental power grid verificationAbhishek, Farid N. Najm. 151-156 [doi]
• Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICsXin Zhao, Michael Scheuermann, Sung Kyu Lim. 157-162 [doi]
• Tracking appliance usage information in residential settings using off-the-shelf low-frequency metersDeokwoo Jung, Andreas Savvides, Athanasios Bamis. 163-168 [doi]
• Implementing an FPGA system for real-time intent recognition for prosthetic legsXiaorong Zhang, He Huang, Qing Yang. 169-175 [doi]
• Statistical design and optimization for adaptive post-silicon tuning of MEMS filtersFa Wang, Gokce Keskin, Andrew Phelps, Jonathan Rotner, Xin Li, Gary K. Fedder, Tamal Mukherjee, Lawrence T. Pileggi. 176-181 [doi]
• th and mobility variations in LTPS TFTs for non-uniformity calibration of active-matrix OLED displaysG. Reza Chaji, Javid Jaffari. 182-187 [doi]
• Towards fault-tolerant embedded systems with imperfect fault detectionJia Huang, Kai Huang, Andreas Raabe, Christian Buckl, Alois Knoll. 188-196 [doi]
• Steady-state dynamic temperature analysis and reliability optimization for embedded multiprocessor systemsIvan Ukhov, Min Bao, Petru Eles, Zebo Peng. 197-204 [doi]
• Considering diagnosis functionality during automatic system-level design of automotive networksMichael Eberl, Michael Glaß, Jürgen Teich, Ulrich Abelein. 205-213 [doi]
• Meta-Cure: a reliability enhancement strategy for metadata in NAND flash memory storage systemsYi Wang 0003, Luis Angel D. Bathen, Nikil D. Dutt, Zili Shao. 214-219 [doi]
• EDA for secure and dependable cybercars: challenges and opportunitiesFarinaz Koushanfar, Ahmad-Reza Sadeghi, Hervé Seudie. 220-228 [doi]
• Software controlled cell bit-density to improve NAND flash lifetimeXavier Jimenez, David Novo, Paolo Ienne. 229-234 [doi]
• Observational wear leveling: an efficient algorithm for flash memory managementChundong Wang, Weng-Fai Wong. 235-242 [doi]
• Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPsAdwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar Iyer, Chita R. Das. 243-252 [doi]
• Point and discard: a hard-error-tolerant architecture for non-volatile last level cachesJue Wang, Xiangyu Dong, Yuan Xie. 253-258 [doi]
• Self-aware computing in the Angstrom processorHenry Hoffmann, Jim Holt, George Kurian, Eric Lau, Martina Maggio, Jason E. Miller, Sabrina M. Neuman, Mahmut E. Sinangil, Yildiz Sinangil, Anant Agarwal, Anantha P. Chandrakasan, Srinivas Devadas. 259-264 [doi]
• The case for elastic operating system services in fosLamia Youseff, Nathan Beckmann, Harshad Kasture, Charles Gruenwald III, David Wentzlaff, Anant Agarwal. 265-270 [doi]
• A compiler and runtime for heterogeneous computingJoshua S. Auerbach, David F. Bacon, Ioana Burcea, Perry Cheng, Stephen J. Fink, Rodric M. Rabbah, Sunil Shukla. 271-276 [doi]
• The HELIX project: overview and directionsSimone Campanoni, Timothy M. Jones, Glenn H. Holloway, Gu-Yeon Wei, David Brooks. 277-282 [doi]
• Exploring sub-20nm FinFET design with predictive technology modelsSaurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao. 283-288 [doi]
• Fast nonlinear model order reduction via associated transforms of high-order volterra transfer functionsYang Zhang, Haotian Liu, Qing Wang, Neric Fong, Ngai Wong. 289-294 [doi]
• AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuitsYangfeng Su, Fan Yang, Xuan Zeng. 295-300 [doi]
• BLAST: efficient computation of nonlinear delay sensitivities in electronic and biological networks using barycentric Lagrange enabled transient adjoint analysisArie Meir, Jaijeet S. Roychowdhury. 301-310 [doi]
• DAE2FSM: automatic generation of accurate discrete-time logical abstractions for continuous-time circuit dynamicsKarthik V. Aadithya, Jaijeet S. Roychowdhury. 311-316 [doi]
• Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICsMoongon Jung, David Z. Pan, Sung Kyu Lim. 317-326 [doi]
• Symbolic model checking on SystemC designsChun-Nan Chou, Yen-Sheng Ho, Chiao Hsieh, Chung-Yang (Ric) Huang. 327-333 [doi]
• System verification of concurrent RTL modules by compositional path predicate abstractionJoakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz. 334-343 [doi]
• Equivalence checking for behaviorally synthesized pipelinesKecheng Hao, Sandip Ray, Fei Xie. 344-349 [doi]
• Proving correctness of regular expression acceleratorsMitra Purandare, Kubilay Atasu, Christoph Hagleitner. 350-355 [doi]
• Sciduction: combining induction, deduction, and structure for verification and synthesisSanjit A. Seshia. 356-365 [doi]
• Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfacesSahar Foroutan, Abbas Sheibanyrad, Frédéric Pétrot. 366-375 [doi]
• Attackboard: a novel dependency-aware traffic generator for exploring NoC design spaceYoshi Shih-Chieh Huang, Yu-Chi Chang, Tsung-Chan Tsai, Yuan-Ying Chang, Chung-Ta King. 376-381 [doi]
• Towards graceful aging degradation in NoCs through an adaptive routing algorithmKshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy. 382-391 [doi]
• Explicit modeling of control and data for improved NoC router estimationAndrew B. Kahng, Bill Lin, Siddhartha Nath. 392-397 [doi]
• Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOISunghyun Park, Tushar Krishna, Chia-Hsin Owen Chen, Bhavya Daya, Anantha Chandrakasan, Li-Shiuan Peh. 398-405 [doi]
• High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of serviceSudhir Satpathy, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David Blaauw. 406-411 [doi]
• WCET-centric partial instruction cache lockingHuping Ding, Yun Liang, Tulika Mitra. 412-420 [doi]
• Worst-case execution time analysis for parallel run-time monitoringDaniel Lo, G. Edward Suh. 421-429 [doi]
• Conforming the runtime inputs for hard real-time embedded systemsKai Huang, Gang Chen, Christian Buckl, Alois Knoll. 430-436 [doi]
• STM concurrency control for embedded real-time software with tighter time boundsMohammed El-Shambakey, Binoy Ravindran. 437-446 [doi]
• HaVOC: a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memoriesLuis Angel D. Bathen, Nikil Dutt. 447-452 [doi]
• Age-based PCM wear leveling with nearly zero search costChi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, Cheng-Yuan Michael Wang. 453-458 [doi]
• Algorithms and data structures for fast and good VLSI routingMichael Gester, Dirk Müller 0003, Tim Nieberg, Christian Panten, Christian Schulte 0002, Jens Vygen. 459-464 [doi]
• Guiding a physical design closure system to produce easier-to-route designs with more predictable timingZhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou. 465-470 [doi]
• Rule agnostic routing by using design fabricsGyuszi Suto. 471-475 [doi]
• Making non-volatile nanomagnet logic non-volatileAaron Dingler, Steve Kurtz, Michael T. Niemier, Xiaobo Sharon Hu, György Csaba, Joseph Nahas, Wolfgang Porod, Gary H. Bernstein, Peng Li, Vjiay Karthik Sankar. 476-485 [doi]
• mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devicesDaniel Morris, David Bromberg, Jian-Gang (Jimmy) Zhu, Larry T. Pileggi. 486-491 [doi]
• Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architectureSang Phill Park, Sumeet Kumar Gupta, Niladri Narayan Mojumder, Anand Raghunathan, Kaushik Roy. 492-497 [doi]
• Hardware realization of BSB recall function using memristor crossbar arraysMiao Hu, Hai Li, Qing Wu, Garrett S. Rose. 498-503 [doi]
• A methodology for energy-quality tradeoff using imprecise hardwareJiawei Huang, John Lach, Gabriel Robins. 504-509 [doi]
• On the exploitation of the inherent error resilience of wireless systems under unreliable siliconGeorgios Karakonstantis, Christoph Roth, Christian Benkeser, Andreas Burg. 510-515 [doi]
• Near-optimal, dynamic module reconfiguration in a photovoltaic system to combat partial shading effectsXue Lin, Yanzhi Wang, Siyu Yue, Donghwa Shin, Naehyuck Chang, Massoud Pedram. 516-521 [doi]
• Networked architecture for hybrid electrical energy storage systemsYounghyun Kim, Sangyoung Park, Naehyuck Chang, Qing Xie, Yanzhi Wang, Massoud Pedram. 522-528 [doi]
• A new uncertainty budgeting based method for robust analog/mixed-signal designJin Sun, Priyank Gupta, Janet Meiling Wang Roveda. 529-535 [doi]
• Variability-aware, discrete optimization for analog circuitsSeobin Jung, Yunju Choi, Jaeha Kim. 536-541 [doi]
• Efficient multi-objective synthesis for microwave components based on computational intelligence techniquesBo Liu, Hadi Aliakbarian, Soheil Radiom, Guy A. E. Vandenbosch, Georges G. E. Gielen. 542-548 [doi]
• Non-uniform multilevel analog routing with matching constraintsHung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang. 549-554 [doi]
• X-tracer: a reconfigurable X-tolerant trace compressor for silicon debugFeng Yuan, Xiao Liu, Qiang Xu. 555-560 [doi]
• Quick detection of difficult bugs for effective post-silicon validationDavid Lin, Ted Hong, Farzan Fallah, Nagib Hakim, Subhasish Mitra. 561-566 [doi]
• Test-data volume optimization for diagnosisHongfei Wang, Osei Poku, Xiaochun Yu, Sizhe Liu, Ibrahima Komara, Ronald D. Blanton. 567-572 [doi]
• Invariance-based concurrent error detection for advanced encryption standardXiaofei Guo, Ramesh Karri. 573-578 [doi]
• Accelerating neuromorphic vision algorithms for recognitionAhmed Al-Maashri, Michael DeBole, Matthew Cotter, Nandhini Chandramoorthy, Yang Xiao, Vijaykrishnan Narayanan, Chaitali Chakrabarti. 579-584 [doi]
• Statistical memristor modeling and case study in neuromorphic computingRobinson E. Pino, Hai Helen Li, Yiran Chen, Miao Hu, Beiye Liu. 585-590 [doi]
• Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technologyQiang Ma 0002, Hongbo Zhang, Martin D. F. Wong. 591-596 [doi]
• GDRouter: interleaved global routing and detailed routing for ultimate routabilityYanheng Zhang, Chris Chu. 597-602 [doi]
• Standard cell routing via boolean satisfiabilityNikolai Ryzhenko, Steven Burns. 603-612 [doi]
• An efficient algorithm for multi-layer obstacle-avoiding rectilinear Steiner tree constructionChih-Hung Liu, I.-Che Chen, D. T. Lee. 613-622 [doi]
• Avoiding game over: bringing design to the next levelOfer Shacham, Sameh Galal, Sabarish Sankaranarayanan, Megan Wachs, John Brunhaver, Artem Vassiliev, Mark Horowitz, Andrew Danowitz, Wajahat Qadeer, Stephen Richardson. 623-629 [doi]
• PowerField: a transient temperature-to-power technique based on Markov random field theorySeungwook Paek, Seok Hwan Moon, Wongyu Shin, Jaehyeong Sim, Lee-Sup Kim. 630-635 [doi]
• EigenMaps: algorithms for optimal thermal maps extraction and sensor placement on multicore processorsJuri Ranieri, Alessandro Vincenzi, Amina Chebira, David Atienza, Martin Vetterli. 636-641 [doi]
• An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoringHuapeng Zhou, Xin Li, Chen-Yong Cher, Eren Kursun, Haifeng Qian, Shi-Chune Yao. 642-647 [doi]
• Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraintsJie Meng, Katsutoshi Kawakami, Ayse Kivilcim Coskun. 648-655 [doi]
• Static dataflow with access patterns: semantics and analysisArkadeb Ghosal, Rhishikesh Limaye, Kaushik Ravindran, Stavros Tripakis, Ankita Prasad, Guoqiang Wang, Trung N. Tran, Hugo A. Andrade. 656-663 [doi]
• Executing synchronous dataflow graphs on a SPM-based multicore architectureJunchul Choi, Hyunok Oh, Sungchan Kim, Soonhoi Ha. 664-671 [doi]
• System-level synthesis of memory architecture for stream processing sub-systems of a MPSoCGlenn Leary, Weijia Che, Karam S. Chatha. 672-677 [doi]
• Courteous cache sharing: being nice to others in capacity managementAkbar Sharifi, Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin. 678-687 [doi]
• A hybrid approach to cyber-physical systems verificationPratyush Kumar, Dip Goswami, Samarjit Chakraborty, Anuradha Annaswamy, Kai Lampka, Lothar Thiele. 688-696 [doi]
• Reliable computing with ultra-reduced instruction set co-processorsAravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren D. Patel, Mahesh V. Tripunitara, Siddharth Garg. 697-702 [doi]
• Identification of recovered ICs using fingerprints from a light-weight on-chip sensorXuehui Zhang, Nicholas Tuzzio, Mohammad Tehranipoor. 703-708 [doi]
• Confidentiality preserving integer programming for global routingHamid Shojaei, Azadeh Davoodi, Parmeswaran Ramanathan. 709-716 [doi]
• Design tools for artificial nervous systemsLouis Scheffer. 717-722 [doi]
• Dynamic river network simulation at large scaleFrank Liu, Ben R. Hodges. 723-728 [doi]
• Humans for EDA and EDA for humansValeria Bertacco. 729-733 [doi]
• Application of logic synthesis to the understanding and cure of genetic diseasesPey-Chang Kent Lin, Sunil P. Khatri. 734-740 [doi]
• Exploiting die-to-die thermal coupling in 3D IC placementKrit Athikulwongse, Mohit Pathak, Sung Kyu Lim. 741-746 [doi]
• ComPLx: A Competitive Primal-dual Lagrange Optimization for Global PlacementMyung-Chul Kim, Igor L. Markov. 747-752 [doi]
• PADE: a high-performance placer with automatic datapath extraction and evaluation through high dimensional data learningSamuel I. Ward, Duo Ding, David Z. Pan. 756-761 [doi]
• Structure-aware placement for datapath-intensive circuit designsSheng Chou, Meng-Kai Hsu, Yao-Wen Chang. 762-767 [doi]
• GLARE: global and local wiring aware routability evaluationYaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar. 768-773 [doi]
• The DAC 2012 routability-driven placement contest and benchmark suiteNatarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei. 774-782 [doi]
• Removing overhead from high-level interfacesKyle Kelley, Megan Wachs, John P. Stevenson, Stephen Richardson, Mark Horowitz. 783-789 [doi]
• On the asymptotic costs of multiplexer-based reconfigurabilityJohnathan York, Derek Chiou. 790-795 [doi]
• SALSA: systematic logic synthesis of approximate circuitsSwagath Venkataramani, Amit Sabne, Vivek J. Kozhikkottu, Kaushik Roy, Anand Raghunathan. 796-801 [doi]
• Timing ECO optimization using metal-configurable gate-array spare cellsHua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang. 802-807 [doi]
• Early prediction of NBTI effects using RTL source code analysisJayanand Asok Kumar, Kenneth M. Butler, HeeSoo Kim, Shobha Vasudevan. 808-813 [doi]
• Generalized SAT-sweeping for post-mapping optimizationTobias Welp, Smita Krishnaswamy, Andreas Kuehlmann. 814-819 [doi]
• Accuracy-configurable adder for approximate arithmetic designsAndrew B. Kahng, Seokhyeong Kang. 820-825 [doi]
• Recovery-based design for variation-tolerant SoCsVivek J. Kozhikkottu, Sujit Dey, Anand Raghunathan. 826-833 [doi]
• A hybrid NoC design for cache coherence optimization for chip multiprocessorsHui Zhao, Ohyoung Jang, Wei Ding, Yuanrui Zhang, Mahmut T. Kandemir, Mary Jane Irwin. 834-842 [doi]
• Architecture support for accelerator-rich CMPsJason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman. 843-849 [doi]
• A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoCMin Kyu Jeong, Mattan Erez, Chander Sudanthi, Nigel C. Paver. 850-855 [doi]
• Metronome: operating system level performance management via self-adaptive computingFilippo Sironi, Davide B. Bartolini, Simone Campanoni, Fabio Cancare, Henry Hoffmann, Donatella Sciuto, Marco D. Santambrogio. 856-865 [doi]
• Adaptive power management of on-chip video memory for multiview video codingMuhammad Shafique, Bruno Zatt, Fabio Leandro Walter, Sergio Bampi, Jörg Henkel. 866-875 [doi]
• Heterogeneous multi-channel: fine-grained DRAM control for both system performance and power efficiencyGuangfei Zhang, Huandong Wang, Xinke Chen, Shuai Huang, Peng Li. 876-881 [doi]
• Joint management of RAM and flash memory with access pattern considerationsPo-Chun Huang, Yuan-Hao Chang, Tei-Wei Kuo. 882-887 [doi]
• Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPUDongki Kim, Sungkwang Lee, JaeWoong Chung, Daehyun Kim, Dong Hyuk Woo, Sungjoo Yoo, Sunggu Lee. 888-896 [doi]
• Write performance improvement by hiding R drift latency in phase-change RAMYoungsik Kim, Sungjoo Yoo, Sunggu Lee. 897-906 [doi]
• Constructing large and fast multi-level cell STT-MRAM based cache for embedded processorsLei Jiang, Bo Zhao, Youtao Zhang, Jun Yang 0002. 907-912 [doi]
• Incorrect systems: it's not the problem, it's the solutionChristoph M. Kirsch, Hannes Payer. 913-917 [doi]
• On software design for stochastic processorsJoseph Sloan, John Sartori, Rakesh Kumar. 918-923 [doi]
• What to do about the end of Moore's law, probably!Krishna V. Palem, Lingamneni Avinash. 924-929 [doi]
• Obtaining and reasoning about good enough softwareMartin C. Rinard. 930-935 [doi]
• Improving gate-level simulation accuracy when unknowns existKai-Hui Chang, Chris Browy. 936-940 [doi]
• Automated feature localization for hardware designs using coverage metricsJan Malburg, Alexander Finder, Görschwin Fey. 941-946 [doi]
• Path directed abstraction and refinement in SAT-based design debuggingBrian Keng, Andreas G. Veneris. 947-954 [doi]
• Checking architectural outputs instruction-by-instruction on acceleration platformsDebapriya Chatterjee, Anatoly Koyfman, Ronny Morad, Avi Ziv, Valeria Bertacco. 955-961 [doi]
• Standard cell sizing for subthreshold operationBo Liu, Maryam Ashouei, Jos Huisken, José Pineda de Gyvez. 962-967 [doi]
• Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuitsMingoo Seok. 968-973 [doi]
• Regaining throughput using completion detection for error-resilient, near-threshold logicJoseph Crop, Robert Pawlowski, Patrick Chiang. 974-979 [doi]
• Process variation in near-threshold wide SIMD architecturesSangwon Seo, Ronald G. Dreslinski, Mark Woh, Yongjun Park, Chaitali Chakrabarti, Scott A. Mahlke, David Blaauw, Trevor N. Mudge. 980-987 [doi]
• Run-time power-down strategies for real-time SDRAM memory controllersKarthik Chandrasekar 0001, Benny Akesson, Kees Goossens. 988-993 [doi]
• Embedding statistical tests for on-chip dynamic voltage and temperature monitoringLionel Vincent, Philippe Maurine, Suzanne Lesecq, Edith Beigné. 994-999 [doi]
• Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devicesXiang Chen, Jian Zheng, Yiran Chen, Mengying Zhao, Chun Jason Xue. 1000-1005 [doi]
• Traffic-aware power optimization for network applications on multicore serversJilong Kuang, Laxmi N. Bhuyan, Raymond Klefstad. 1006-1011 [doi]
• Alternate hammering test for application-specific DRAMs and an industrial case studyRei-Fu Huang, Hao-Yu Yang, Mango Chia-Tso Chao, Shih-Chin Lin. 1012-1017 [doi]
• Goal-oriented stimulus generation for analog circuitsSeyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan. 1018-1023 [doi]
• TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocationFangming Ye, Krishnendu Chakrabarty. 1024-1030 [doi]
• Small delay testing for TSVs in 3-D ICsShi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai. 1031-1036 [doi]
• Circuit and system design guidelines for ultra-low power sensor nodesYoonmyung Lee, Yejoong Kim, Dongmin Yoon, David Blaauw, Dennis Sylvester. 1037-1042 [doi]
• Design exploration of energy-performance trade-offs for wireless sensor networksIvan Beretta, Francisco J. Rincón, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana, David Atienza. 1043-1048 [doi]
• Energy harvesting and power management for autonomous sensor nodesJean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Jérôme Willemin, Christian Piguet. 1049-1054 [doi]
• Functional timing analysis made fast and generalYi-Ting Chung, Jie-Hong Roland Jiang. 1055-1060 [doi]
• Timing analysis with nonseparable statistical and deterministic variationsVladimir Zolotov, Debjit Sinha, Jeffrey G. Hemmett, Eric A. Foreman, Chandu Visweswariah, Jinjun Xiong, Jeremy Leitzen, Natesan Venkateswaran. 1061-1066 [doi]
• max/min operation: concept and applications to timingDebjit Sinha, Chandu Visweswariah, Natesan Venkateswaran, Jinjun Xiong, Vladimir Zolotov. 1067-1073 [doi]
• Predicting timing violations through instruction-level path sensitization analysisSanghamitra Roy, Koushik Chakraborty. 1074-1081 [doi]
• A chip-package-board co-design methodologyHsu-Chieh Lee, Yao-Wen Chang. 1082-1087 [doi]
• Obstacle-avoiding free-assignment routing for flip-chip designsPo-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen. 1088-1093 [doi]
• Clock tree synthesis with methodology of re-use in 3D ICFu-Wei Chen, TingTing Hwang. 1094-1099 [doi]
• Can pin access limit the footprint scaling?Xiang Qiu, Malgorzata Marek-Sadowska. 1100-1106 [doi]
• Yield estimation via multi-conesRouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif. 1107-1112 [doi]
• Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuitsChin-Cheng Kuo, Wei-Yi Hu, Yi-Hung Chen, Jui-Feng Kuan, Yi-Kan Cheng. 1113-1118 [doi]
• Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly support-circuit preconditionersXueqian Zhao, Zhuo Feng. 1119-1124 [doi]
• Sparse LU factorization for parallel circuit simulation on GPULing Ren, Xiaoming Chen, Yu Wang 0002, Chenxi Zhang, Huazhong Yang. 1125-1130 [doi]
• Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypseMichael B. Taylor. 1131-1136 [doi]
• Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applicationsDiego Melpignano, Luca Benini, Eric Flamand, Bruno Jego, Thierry Lepley, Germain Haugou, Fabien Clermidy, Denis Dutoit. 1137-1142 [doi]
• Big.LITTLE system architecture from ARM: saving power through heterogeneous multiprocessing and task context migrationBrian Jeff. 1143-1146 [doi]
• Assessing the performance limits of parallelized near-threshold computingNathaniel Ross Pinckney, Korey Sewell, Ronald G. Dreslinski, David Fick, Trevor N. Mudge, Dennis Sylvester, David Blaauw. 1147-1152 [doi]
• Near-threshold voltage (NTV) design: opportunities and challengesHimanshu Kaul, Mark Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar. 1153-1158 [doi]
• Near-threshold operation for power-efficient computing?: it depends..Leland Chang, Wilfried Haensch. 1159-1163 [doi]
• Not so fast my friend: is near-threshold computing the answer for power reduction of wireless devices?Matt Severson, Kendrick Yuen, Yang Du. 1164-1166 [doi]
• Accurate process-hotspot detection using critical design rule extractionYen-Ting Yu, Ya-Chung Chan, Subarna Sinha, Iris Hui-Ru Jiang, Charles Chiang. 1167-1172 [doi]
• Improved tangent space based distance metric for accurate lithographic hotspot classificationJing Guo, Fan Yang, Subarna Sinha, Charles Chiang, Xuan Zeng. 1173-1178 [doi]
• Simultaneous flare level and flare variation minimization with dummification in EUVLShao-Yun Fang, Yao-Wen Chang. 1179-1184 [doi]
• A novel layout decomposition algorithm for triple patterning lithographyShao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen. 1185-1190 [doi]
• PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis methodWujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang 0002, Yuan Xie. 1191-1196 [doi]
• Exploiting narrow-width values for process variation-tolerant 3-D microprocessorsJoonho Kong, Sung Woo Chung. 1197-1206 [doi]
• Hardware synthesis of recursive functions through partial stream rewritingLars Middendorf, Christophe Bobda, Christian Haubelt. 1207-1215 [doi]
• Chisel: constructing hardware in a Scala embedded languageJonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic. 1216-1225 [doi]
• Specification and synthesis of hardware checkpointing and rollback mechanismsCarven Chan, Daniel Schwartz-Narbonne, Divjyot Sethi, Sharad Malik. 1226-1232 [doi]
• Optimizing memory hierarchy allocation with loop transformations for high-level synthesisJason Cong, Peng Zhang, Yi Zou. 1233-1238 [doi]
• A metric for layout-friendly microarchitecture optimization in high-level synthesisJason Cong, Bin Liu. 1239-1244 [doi]
• Computer generation of streaming sorting networksMarcela Zuluaga, Peter A. Milder, Markus Püschel. 1245-1253 [doi]
• CrowdMine: towards crowdsourced human-assisted verificationWenchao Li, Sanjit A. Seshia, Somesh Jha. 1254-1255 [doi]
• Extracting design information from natural language specificationsIan G. Harris. 1256-1257 [doi]
• Material implication in CMOS: a new kind of logicElkim Roa, Wu-Hsin Chen, Byunghoo Jung. 1258-1259 [doi]
• Boolean satisfiability using noise based logicPey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri. 1260-1261 [doi]
• Cognitive computing with spin-based neural networksMrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy. 1262-1263 [doi]
• Capacitance of TSVs in 3-D stacked chips a problem?: not for neuromorphic systems!Antoine Joubert, Marc Duranton, Bilel Belhadj, Olivier Temam, Rodolphe Héliot. 1264-1265 [doi]
• Communication-aware mapping of KPN applications onto heterogeneous MPSoCsJerónimo Castrillón, Andreas Tretter, Rainer Leupers, Gerd Ascheid. 1266-1271 [doi]
• Unrolling and retiming of stream applications onto embedded multicore processorsWeijia Che, Karam S. Chatha. 1272-1277 [doi]
• Exploiting spatiotemporal and device contexts for energy-efficient mobile embedded systemsBrad K. Donohoo, Chris Ohlsen, Sudeep Pasricha, Charles Anderson. 1278-1283 [doi]
• EPIMap: using epimorphism to map applications on CGRAsMahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula. 1284-1291 [doi]
• Instruction scheduling for reliability-aware compilationSemeen Rehman, Muhammad Shafique, Jörg Henkel. 1292-1300 [doi]
• Compiling for energy efficiency on timing speculative processorsJohn Sartori, Rakesh Kumar. 1301-1308 [doi]