Abstract is missing.
- Don't-Care-Based Node Minimization for Threshold Logic NetworksYung-Chih Chen, Hao-Ju Chang, Li-Cheng Zheng. 1-6 [doi]
- Input-Dependent Edge-Cloud Mapping of Recurrent Neural Networks InferenceDaniele Jahier Pagliari, Roberta Chiaro, Yukai Chen, Sara Vinco, Enrico Macii, Massimo Poncino. 1-6 [doi]
- TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRAMingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin. 1-6 [doi]
- TrojDRL: Evaluation of Backdoor Attacks on Deep Reinforcement LearningPanagiota Kiourti, Kacper Wardega, Susmit Jha, Wenchao Li. 1-6 [doi]
- 3D CNN Acceleration on FPGA using Hardware-Aware PruningMengshu Sun, Pu Zhao, Mehmet Güngör, Massoud Pedram, Miriam Leeser, Xue Lin. 1-6 [doi]
- FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order OptimizationJiaqi Gu, Zheng Zhao, Chenghao Feng, Wuxi Li, Ray T. Chen, David Z. Pan. 1-6 [doi]
- An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit SynthesisShuhan Zhang, Fan Yang 0001, Dian Zhou, Xuan Zeng 0001. 1-6 [doi]
- *Jianli Chen, Zhipeng Huang 0009, Ye Huang, Wenxing Zhu, Jun Yu, Yao-Wen Chang. 1-6 [doi]
- Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant CircuitYan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao 0001, Jun Han 0003, Xu Cheng 0002, Mehdi B. Tahoori, Xiaoyang Zeng. 1-6 [doi]
- AHEC: End-to-end Compiler Framework for Privacy-preserving Machine Learning AccelerationHuili Chen, Rosario Cammarota, Felipe Valencia, Francesco Regazzoni 0001, Farinaz Koushanfar. 1-6 [doi]
- DPCP-p: A Distributed Locking Protocol for Parallel Real-Time TasksMaolin Yang, Ze-Wei Chen, Xu Jiang, Nan Guan, Hang Lei. 1-6 [doi]
- Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCsJan Spieck, Stefan Wildermann, Jürgen Teich. 1-6 [doi]
- CoinPurse: A Device-Assisted File System with Dual InterfacesZhe Yang, Youyou Lu, Erci Xu, Jiwu Shu. 1-6 [doi]
- Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-ChipYu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang. 1-6 [doi]
- PCNN: Pattern-based Fine-Grained Regular Pruning Towards Optimizing CNN AcceleratorsZhanhong Tan, Jiebo Song, Xiaolong Ma, Sia Huat Tan, Hongyang Chen, Yuanqing Miao, Yifu Wu, Shaokai Ye, Yanzhi Wang, Dehui Li, Kaisheng Ma. 1-6 [doi]
- Runtime Trust Evaluation and Hardware Trojan Detection Using On-Chip EM SensorsJiaji He, Xiaolong Guo, Haocheng Ma, Yanjiang Liu, Yiqiang Zhao, Yier Jin. 1-6 [doi]
- Q-PIM: A Genetic Algorithm based Flexible DNN Quantization Method and Application to Processing-In-Memory PlatformYun Long, Edward Lee, Daehyun Kim, Saibal Mukhopadhyay. 1-6 [doi]
- Late Breaking Results: A Neural Network that Routes ICsDmitry Utyamishev, Inna Partin-Vaisband. 1-2 [doi]
- Massively Parallel Approximate Simulation of Hard Quantum CircuitsIgor L. Markov, Aneeqa Fatima, Sergei V. Isakov, Sergio Boixo. 1-6 [doi]
- The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSLBo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig. 1-6 [doi]
- INVITED: Efficient Synthesis of Compact Deep Neural NetworksWenhan Xia, Hongxu Yin, Niraj K. Jha. 1-6 [doi]
- Circuit Learning for Logic Regression on High Dimensional Boolean SpacePei-Wei Chen, Yu-Ching Huang, Cheng-Lin Lee, Jie-Hong Roland Jiang. 1-6 [doi]
- TCIM: Triangle Counting Acceleration With Processing-In-MRAM ArchitectureXueyan Wang, Jianlei Yang 0001, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao. 1-6 [doi]
- 28 Challenge-Response PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge SelectionVikram B. Suresh, Raghavan Kumar, Sanu Mathew. 1-3 [doi]
- PAIR: Pin-aligned In-DRAM ECC architecture using expandability of Reed-Solomon codeSangmok Jeong, SeungYup Kang, Joon-Sung Yang. 1-6 [doi]
- PIM-Assembler: A Processing-in-Memory Platform for Genome AssemblyShaahin Angizi, Naima Ahmed Fahmi, Wei Zhang, Deliang Fan. 1-6 [doi]
- DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAsRui Li, Heng Yu, Weixiong Jiang, Yajun Ha. 1-6 [doi]
- BitPruner: Network Pruning for Bit-serial AcceleratorsXiandong Zhao, Ying Wang, Cheng Liu, Cong Shi, Kaijie Tu, Lei Zhang. 1-6 [doi]
- RTMobile: Beyond Real-Time Mobile Acceleration of RNNs for Speech RecognitionPeiyan Dong, Siyue Wang, Wei Niu, Chengming Zhang, Sheng Lin, Zhengang Li, Yifan Gong, Bin Ren, Xue Lin, Dingwen Tao. 1-6 [doi]
- Robust Design of Large Area Flexible Electronics via Compressed SensingLeilai Shao, Ting Lei, Tsung-Ching Huang, Zhenan Bao, Kwang-Ting Cheng. 1-6 [doi]
- From Homogeneous to Heterogeneous: Leveraging Deep Learning based Power Analysis across DevicesFan Zhang, Bin Shao, Guorui Xu, Bolin Yang, Ziqi Yang, Zhan Qin, Kui Ren 0001. 1-6 [doi]
- Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGAMinjin Tang, Mei Wen, Junzhong Shen, Xiaolei Zhao, Chunyuan Zhang. 1-6 [doi]
- Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum FrequencyLicheng Guo, Jason Lau, Yuze Chi, Jie Wang 0022, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong. 1-6 [doi]
- Learning Concise Models from Long Execution TracesNatasha Yogananda Jeppu, Thomas F. Melham, Daniel Kroening, John O'Leary. 1-6 [doi]
- EMAP: A Cloud-Edge Hybrid Framework for EEG Monitoring and Cross-Correlation Based Real-time Anomaly PredictionBharath Srinivas Prabakaran, Alberto García Jiménez, Germán Moltó Martínez, Muhammad Shafique 0001. 1-6 [doi]
- ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory MultiprocessorAndreas Kurth, Samuel Riedel, Florian Zaruba, Torsten Hoefler, Luca Benini. 1-6 [doi]
- Layer RBER Variation Aware Read Performance Optimization for 3D Flash MemoriesShiqiang Nie, Youtao Zhang, Weiguo Wu, Jun Yang. 1-6 [doi]
- Late Breaking Results: FRIENDS - Finding Related Interesting Events via Neighbor DetectionRaviv Gal, Haim Kermany, Alexander Ivrii, Ziv Nevo, Avi Ziv. 1-2 [doi]
- Learning to Predict IR Drop with Effective Training for ReRAM-based Neural Network HardwareSugil Lee, Giju Jung, Mohammed E. Fouda, Jongeun Lee, Ahmed M. Eltawil, Fadi J. Kurdahi. 1-6 [doi]
- Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit OverheadHyungJun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim. 1-6 [doi]
- Predictable Memory-CPU Co-Scheduling with Support for Latency-Sensitive TasksDaniel Casini, Paolo Pazzaglia, Alessandro Biondi, Marco Di Natale, Giorgio C. Buttazzo. 1-6 [doi]
- Tight Compression: Compressing CNN Model Tightly Through Unstructured Pruning and Simulated Annealing Based PermutationXizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui. 1-6 [doi]
- Stannis: Low-Power Acceleration of DNN Training Using Computational Storage DevicesAli Heydari Gorji, Mahdi Torabzadehkashi, Siavash Rezaei, Hossein Bobarshad, Vladimir Castro Alves, Pai H. Chou. 1-6 [doi]
- A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore ArchitecturesHao Zheng 0005, Ke Wang 0030, Ahmed Louri. 1-6 [doi]
- A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip TrainingHongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu. 1-6 [doi]
- Hardware-assisted Service Live Migration in Resource-limited Edge Computing SystemsZhe Zhou, Xintong Li, Xiaoyang Wang 0006, Zheng Liang, Guangyu Sun 0003, Guojie Luo. 1-6 [doi]
- Invited: Chipyard - An Integrated SoC Research and Implementation EnvironmentAlon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert J. Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt 0001, John Wright, Jerry Zhao, Jonathan Bachrach, Yakun Sophia Shao, Borivoje Nikolic, Krste Asanovic. 1-6 [doi]
- Extending the RISC-V ISA for Efficient RNN-based 5G Radio Resource ManagementRenzo Andri, Tomas Henriksson, Luca Benini. 1-6 [doi]
- Imperceptible Misclassification Attack on Deep Learning Accelerator by Glitch InjectionWenye Liu, Chip-Hong Chang, Fan Zhang, Xiaoxuan Lou. 1-6 [doi]
- Towards State-Aware Computation in ReRAM Neural NetworksYintao He, Ying Wang 0001, Xiandong Zhao, Huawei Li, Xiaowei Li 0001. 1-6 [doi]
- Access Characteristic Guided Partition for Read Performance Improvement on Solid State DrivesYina Lv, Liang Shi, Qiao Li 0001, Chun Jason Xue, Edwin H.-M. Sha. 1-6 [doi]
- ICS Protocol Fuzzing: Coverage Guided Packet Crack and GenerationZhengxiong Luo, Feilong Zuo, Yuheng Shen, Xun Jiao, Wanli Chang 0001, Yu Jiang. 1-6 [doi]
- Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power OptimizationChien Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang. 1-2 [doi]
- Navigator: Dynamic Multi-kernel Scheduling to Improve GPU PerformanceJiho Kim, John Kim, Yongjun Park. 1-6 [doi]
- Time-Division Multiplexing Based System-Level FPGA Routing for Logic VerificationPeng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Yu, Yao-Wen Chang. 1-6 [doi]
- A Model Checking-based Analysis Framework for Systems Biology ModelsBing Liu, Sara Safa. 1-6 [doi]
- Seesaw: End-to-end Dynamic Sensing for IoT using Machine LearningVidushi Goyal, Valeria Bertacco, Reetuparna Das. 1-19 [doi]
- Factored Radix-8 Systolic Array for Tensor ProcessingInayat Ullah, Kashif Inayat, Joon-Sung Yang, Jaeyong Chung. 1-6 [doi]
- TEVoT: Timing Error Modeling of Functional Units under Dynamic Voltage and Temperature VariationsXun Jiao, Dongning Ma, Wanli Chang 0001, Yu Jiang 0001. 1-6 [doi]
- Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-PrecisionKyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park 0001. 1-6 [doi]
- Deep Learning Multi-Channel Fusion Attack Against Side-Channel Protected HardwareBenjamin Hettwer, Daniel Fennes, Sebastien Leger, Jan Richter-Brockmann, Stefan Gehrer, Tim Güneysu. 1-6 [doi]
- TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICsYi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, Sung Kyu Lim. 1-6 [doi]
- Balancing Efficiency and Flexibility for DNN Acceleration via Temporal GPU-Systolic Array IntegrationCong Guo, Yangjie Zhou 0001, Jingwen Leng, Yuhao Zhu 0001, Zidong Du, Quan Chen 0002, Chao Li 0009, Bin Yao 0002, Minyi Guo. 1-6 [doi]
- Prive-HD: Privacy-Preserved Hyperdimensional ComputingBehnam Khaleghi, Mohsen Imani, Tajana Rosing. 1-6 [doi]
- WET: Write Efficient Loop Tiling for Non-Volatile Main MemoryMohammad A. Alshboul, James Tuck, Yan Solihin. 1-6 [doi]
- ZENCO: Zero-bytes based ENCOding for Non-Volatile Buffers in On-Chip InterconnectsKhushboo Rani, Hemangee K. Kapoor. 1-6 [doi]
- A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar ArraysArman Kazemi, Cristobal Alessandri, Alan C. Seabaugh, Xiaobo Sharon Hu, Michael T. Niemier, Siddharth Joshi. 1-6 [doi]
- GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor CoresZhuoran Song, Jianfei Wang, Tianjian Li, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing. 1-6 [doi]
- Deep Learning-Driven Simultaneous Layout Decomposition and Mask OptimizationWei Zhong, Shuxiang Hu, Yuzhe Ma, Haoyu Yang, Xiuyuan Ma, Bei Yu 0001. 1-6 [doi]
- PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory ArchitectureChaoqun Chu, Yanzhi Wang, Yilong Zhao, Xiaolong Ma, Shaokai Ye, Yunyan Hong, Xiaoyao Liang, Yinhe Han, Li Jiang. 1-6 [doi]
- Opportunistic Intermittent Control with Safety Guarantees for Autonomous SystemsChao Huang, Shichao Xu, Zhilu Wang, Shuyue Lan, Wenchao Li, Qi Zhu 0002. 1-6 [doi]
- BrezeFlow: Unified Debugger for Android CPU Power Governors and Schedulers on Edge DevicesAlexander Hoffman, Anuj Pathania, Philipp H. Kindt, Samarjit Chakraborty, Tulika Mitra. 1-6 [doi]
- A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical RoutingYu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang. 1-6 [doi]
- A Pragmatic Approach to On-device Incremental Learning System with Selective Weight UpdatesJaekang Shin, Seungkyu Choi, YeongJae Choi, Lee-Sup Kim. 1-6 [doi]
- Best of Both Worlds: AutoML Codesign of a CNN and its Hardware AcceleratorMohamed S. Abdelfattah, Lukasz Dudziak, Thomas C. P. Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane. 1-6 [doi]
- Late Breaking Results: Building an On-Chip Deep Learning Memory Hierarchy Brick by BrickIsak Edo Vivancos, Sayeh Sharify, Milos Nikolic, Ciaran Bannon, Mostafa Mahmoud, Alberto Delmas Lascorz, Andreas Moshovos. 1-2 [doi]
- A-QED Verification of Hardware AcceleratorsEshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Maxwell Strange, Peng Wei 0004, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang, Clark W. Barrett, Subhasish Mitra. 1-6 [doi]
- Unified Architectural Support for Secure and Robust Deep LearningMojan Javaheripi, Huili Chen, Farinaz Koushanfar. 1-6 [doi]
- UEFI Firmware Fuzzing with Simics Virtual PlatformZhenkun Yang, Yuriy Viktorov, Jin Yang, Jiewen Yao, Vincent Zimmer. 1-6 [doi]
- How to Cut Out Expired Data with Nearly Zero Overhead for Solid-State DrivesWei-Lin Wang, Tseng-Yi Chen, Yuan-Hao Chang, Hsin-Wen Wei, Wei Kuan Shih. 1-6 [doi]
- Pythia: Intellectual Property Verification in Zero-KnowledgeDimitris Mouris, Nektarios Georgios Tsoutsos. 1-6 [doi]
- Non-uniform DNN Structured Subnets Sampling for Dynamic InferenceLi Yang, Zhezhi He, Yu Cao, Deliang Fan. 1-6 [doi]
- FlexReduce: Flexible All-reduce for Distributed Deep Learning on Asymmetric Network TopologyJinho Lee, Inseok Hwang 0001, Soham Shah, Minsik Cho. 1-6 [doi]
- MLParest: Machine Learning based Parasitic Estimation for Custom Circuit DesignBrett Shook, Prateek Bhansali, Chandramouli Kashyap, Chirayu Amin, Siddhartha Joshi. 1-6 [doi]
- SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks TrainingPengcheng Dai, Jianlei Yang 0001, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao. 1-6 [doi]
- +-tree-based Data Management Scheme for Key-value Store over SMR-based SSHDYu-Pei Liang, Tseng-Yi Chen, Ching Ho Chi, Hsin-Wen Wei, Wei Kuan Shih. 1-6 [doi]
- Building End-to-End IoT Applications with QoS GuaranteesArne Hamann, Selma Saidi, David Ginthoer, Christian Wietfeld, Dirk Ziegenbein. 1-6 [doi]
- Time Multiplexing via Circuit FoldingPo-Chun Chien, Jie-Hong R. Jiang. 1-6 [doi]
- FCNNLib: An Efficient and Flexible Convolution Algorithm Library on FPGAsQingcheng Xiao, Liqiang Lu, JiaMing Xie, Yun Liang 0001. 1-6 [doi]
- FTDL: A Tailored FPGA-Overlay for Deep Learning with High ScalabilityRunbin Shi, Yuhao Ding, Xuechao Wei, He Li, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding. 1-6 [doi]
- Codar: A Contextual Duration-Aware Qubit Mapping for Various NISQ DevicesHaowei Deng, Yu Zhang 0086, Quanxi Li. 1-6 [doi]
- GRANNITE: Graph Neural Network Inference for Transferable Power EstimationYanqing Zhang, Haoxing Ren, Brucek Khailany. 1-6 [doi]
- STC: Significance-aware Transform-based Codec Framework for External Memory Access ReductionFeng Xiong, Fengbin Tu, Man Shi, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin. 1-6 [doi]
- Prediction Confidence based Low Complexity Gradient Computation for Accelerating DNN TrainingDongyeob Shin, Geonho Kim, Joongho Jo, Jongsun Park 0001. 1-6 [doi]
- Late Breaking Results: LDFSM: A Low-Cost Bit-Stream Generator for Low-Discrepancy Stochastic ComputingSina Asadi, M. Hassan Najafi. 1-2 [doi]
- KFR: Optimal Cache Management with K-Framed Reclamation for Drive-Managed SMR DisksChenlin Ma, Yi Wang, Zhaoyan Shen, Zili Shao. 1-6 [doi]
- Efficiently Exploiting Low Activity Factors to Accelerate RTL SimulationScott Beamer, David Donofrio. 1-6 [doi]
- GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement LearningHanrui Wang 0002, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han. 1-6 [doi]
- On Computing Exact WCRT for DAG Tasks†Jinghao Sun, Feng Li, Nan Guan, Wentao Zhu, Minjie Xiang, Zhishan Guo, Wang Yi 0001. 1-6 [doi]
- INVITED: Computation on Sparse Neural Networks and its Implications for Future HardwareFei Sun, Minghai Qin, Tianyun Zhang, Liu Liu, Yen-Kuang Chen, Yuan Xie. 1-6 [doi]
- A Machine Learning Approach for Reliability-Aware Application Mapping for Heterogeneous MulticoresRafael Billig Tonetto, Hiago M. G. de A. Rocha, Gabriel L. Nazar, Antonio Carlos Schneider Beck. 1-6 [doi]
- PattPIM: A Practical ReRAM-Based DNN Accelerator by Reusing Weight Pattern RepetitionsYuhao Zhang, Zhiping Jia, Yungang Pan, Hongchao Du, Zhaoyan Shen, Mengying Zhao, Zili Shao. 1-6 [doi]
- Transfer Learning-Based Microfluidic Design System for Concentration Generation∗Weiqing Ji, Tsung-Yi Ho, Hailong Yao. 1-6 [doi]
- Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect MitigationJianli Chen, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, Yao-Wen Chang. 1-6 [doi]
- DRAMDig: A Knowledge-assisted Tool to Uncover DRAM Address MappingMinghua Wang, Zhi Zhang 0001, Yueqiang Cheng, Surya Nepal. 1-6 [doi]
- ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based SystemsBharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique 0001. 1-6 [doi]
- Tier-Scrubbing: An Adaptive and Tiered Disk Scrubbing Scheme with Improved MTTD and Reduced CostJi Zhang, Yuanzhang Wang, Yangtao Wang, Ke Zhou 0001, Sebastian Schelter, Ping Huang 0001, Bin Cheng, Yongguang Ji. 1-6 [doi]
- Exploring Inherent Sensor Redundancy for Automotive Anomaly DetectionTianjia He, Lin Zhang, Fanxin Kong, Asif Salekin. 1-6 [doi]
- ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural NetworksHaoxing Ren, George F. Kokai, Walker J. Turner, Ting-Sheng Ku. 1-6 [doi]
- Late Breaking Results: Can You Hear Me? Towards an Ultra Low-Cost Hearing Screening DeviceNils Heitmann, Philipp H. Kindt, Samarjit Chakraborty. 1-2 [doi]
- Romeo: Conversion and Evaluation of HDL Designs in the Encrypted DomainCharles Gouert, Nektarios Georgios Tsoutsos. 1-6 [doi]
- Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire MinimizationAbhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin. 1-2 [doi]
- Improving the Concurrency Performance of Persistent Memory Transactions on MulticoresQing Wang, Youyou Lu, Zhongjie Wu, Fan Yang, Jiwu Shu. 1-6 [doi]
- Symbolic Computer Algebra and SAT Based Information Forwarding for Fully Automatic Divider VerificationChristoph Scholl, Alexander Konrad. 1-6 [doi]
- *Vladimir Herdt, Daniel Große, Rolf Drechsler. 1-6 [doi]
- HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and ImplementationHanchen Ye, Xiaofan Zhang, Zhize Huang, Gengsheng Chen, Deming Chen. 1-6 [doi]
- SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network ArchitecturesNavid Khoshavi, Arman Roohi, Connor Broyles, Saman Sargolzaei, Yu Bi, David Z. Pan. 1-6 [doi]
- RaQu: An automatic high-utilization CNN quantization and mapping framework for general-purpose RRAM AcceleratorSongyun Qu, Bing Li, Ying Wang, Dawen Xu 0002, Xiandong Zhao, Lei Zhang. 1-6 [doi]
- Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUsAhmad M. Radaideh, Paul V. Gratz. 1-6 [doi]
- ROPAD: A Fully Digital Highly Predictive Ring Oscillator Probing Attempt DetectorSeyed Hamidreza Moghadas, Michael Pehl. 1-6 [doi]
- EANeM: Energy-Aware Network Stack Management for Mobile DevicesChungseop Lee, Keonhyuk Lee, Mingoo Kang, Hyukjun Lee. 1-6 [doi]
- GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural NetworksIndranil Chakraborty, Mustafa Fayez Ali, Dong Eun Kim, Aayush Ankit, Kaushik Roy 0001. 1-6 [doi]
- An Efficient Circuit Compilation Flow for Quantum Approximate Optimization AlgorithmMahabubul Alam, Abdullah Ash-Saki, Swaroop Ghosh. 1-6 [doi]
- S-CDA: A Smart Cloud Disk Allocation Approach in Cloud Block Storage SystemHua Wang 0008, Yang Yang 0068, Ping Huang 0001, Yu Zhang, Ke Zhou 0001, Mengling Tao, Bin Cheng. 1-6 [doi]
- Vehicular and Edge Computing for Emerging Connected and Autonomous Vehicle ApplicationsSabur Baidya, Yu-Jen Ku, Hengyu Zhao, Jishen Zhao, Sujit Dey. 1-6 [doi]
- Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple TasksLei Yang, Zheyu Yan, Meng Li 0004, Hyoukjun Kwon, Liangzhen Lai, Tushar Krishna, Vikas Chandra, Weiwen Jiang, Yiyu Shi. 1-6 [doi]
- Efficient Multi-Grained Wear Leveling for Inodes of Persistent Memory File SystemsChaoshu Yang, Duo Liu, Runyu Zhang, Xianzhang Chen, Shun Nie, Fengshun Wang, Qingfeng Zhuge, Edwin H.-M. Sha. 1-6 [doi]
- Stealing Your Data from Compressed Machine Learning ModelsNuo Xu, Qi Liu, Tao Liu, Zihao Liu, Xiaochen Guo, Wujie Wen. 1-6 [doi]
- Probabilistic Error Propagation through Approximated Boolean NetworksJorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich. 1-6 [doi]
- An Efficient and Robust Yield Optimization Method for High-dimensional SRAM CircuitsXiaodong Wang, Tianchen Gu, Changhao Yan, Xiulong Wu, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng 0001. 1-6 [doi]
- PEMACx: A Probabilistic Error Analysis Methodology for Adders with Cascaded Approximate UnitsMuhammad Abdullah Hanif, Rehan Hafiz, Osman Hasan, Muhammad Shafique 0001. 1-6 [doi]
- Learning From A Big Brother - Mimicking Neural Networks in Profiled Side-channel AnalysisDaan van der Valk, Marina Krcek, Stjepan Picek, Shivam Bhasin. 1-6 [doi]
- Hardware Acceleration of Graph Neural NetworksAdam Auten, Matthew Tomei, Rakesh Kumar 0002. 1-6 [doi]
- Statistical Timing Analysis considering Multiple-Input SwitchingDebjit Sinha, Vasant Rao, Chaitanya Peddawad, Michael H. Wood, Jeffrey G. Hemmett, Suriya Skariah, Patrick Williams. 1-6 [doi]
- Compact domain-specific co-processor for accelerating module lattice-based KEMJose Maria Bermudo Mera, Furkan Turan, Angshuman Karmakar, Sujoy Sinha Roy, Ingrid Verbauwhede. 1-6 [doi]
- Latch Clustering for Timing-Power Co-OptimizationChau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang. 1-6 [doi]
- BPNet: Branch-pruned Conditional Neural Network for Systematic Time-accuracy TradeoffKyungchul Park, Chanyoung Oh, Youngmin Yi. 1-6 [doi]
- Towards Purposeful Design Space Exploration of Heterogeneous CGRAs: Clock Frequency EstimationDennis Leander Wolf, Christoph Spang, Christian Hochberger. 1-6 [doi]
- Utilizing Direct Photocurrent Computation and 2D Kernel Scheduling to Improve In-Sensor-Processing EfficiencyHan Xu, Maimaiti Nazhamaiti, Yidong Liu, Fei Qiao, Qi Wei, Xinjun Liu, Huazhong Yang. 1-6 [doi]
- Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net StructuresHsien-Han Cheng, Iris Hui-Ru Jiang, Oscar Ou. 1-6 [doi]
- A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object ClassificationPo-Yao Chuang, Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu. 1-6 [doi]
- DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertYJianqi Chen, Monir Zaman, Yiorgos Makris, R. D. Shawn Blanton, Subhasish Mitra, Benjamin Carrión Schäfer. 1-6 [doi]
- GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link DesignSeungho Han, Sungyu Jeong, Chanho Kim, Hong June Park, Byungsub Kim. 1-6 [doi]
- T2FSNN: Deep Spiking Neural Networks with Time-to-first-spike CodingSeongsik Park, Sei Joon Kim, Byunggook Na, Sungroh Yoon. 1-6 [doi]
- Remote Atomic Extension (RAE) for Scalable High Performance ComputingXi Wang 0009, Brody Williams, John D. Leidel, Alan Ehret, Michel A. Kinsy, Yong Chen. 1-6 [doi]
- A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order ProcessorsMohammad Rahmani Fadiheh, Johannes Müller, Raik Brinkmann, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz. 1-6 [doi]
- INVITED: AI Utopia or Dystopia - On Securing AI PlatformsGhada Dessouky, Patrick Jauernig, Nele Mentens, Ahmad-Reza Sadeghi, Emmanuel Stapf. 1-6 [doi]
- O-2A: Low Overhead DNN Compression with Outlier-Aware ApproximationNguyen-Dong Ho, Minh-Son Le, Ik Joon Chang. 1-6 [doi]
- A Cross-Layer Power and Timing Evaluation Method for Wide Voltage ScalingWenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi. 1-6 [doi]
- Impeccable Circuits IIAein Rezaei Shahmirzadi, Shahram Rasoolzadeh, Amir Moradi 0001. 1-6 [doi]
- Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual PrototypesPascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler. 1-6 [doi]
- High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural NetworksJingyu Wang, Songming Yu, Jinshan Yue, Zhe Yuan, Zhuqing Yuan, Huazhong Yang, Xueqing Li, Yongpan Liu. 1-6 [doi]
- A Simple Cache Coherence Scheme for Integrated CPU-GPU SystemsArdhi Wiratama Baskara Yudha, Reza Pulungan, Henry Hoffmann, Yan Solihin. 1-6 [doi]
- StatSAT: A Boolean Satisfiability based Attack on Logic-Locked Probabilistic CircuitsAnkit Mondal, Michael Zuzak, Ankur Srivastava. 1-6 [doi]
- ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural NetworksAlexander Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Laura Hauenschild, Naveen Shankar Nagaraja, Christian Unger, Walter Stechele. 1-6 [doi]
- Permutation-Write: Optimizing Write Performance and Energy for Skyrmion Racetrack MemoryTsun-Yu Yang, Ming-Chang Yang, Jiawei Li, Wang Kang. 1-6 [doi]
- SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging TechnologiesHe-Teng Zhang, Jie-Hong R. Jiang. 1-6 [doi]
- Adaptive Layout Decomposition with Graph Embedding Neural NetworksWei Li, Jialu Xia, Yuzhe Ma, Jialu Li, Yibo Lin, Bei Yu 0001. 1-6 [doi]
- Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space ExplorationZi Wang, Benjamin Carrión Schäfer. 1-6 [doi]
- AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoCFrancesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgiomaria Cicero, Giorgio C. Buttazzo. 1-6 [doi]
- Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction OffloadingJeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs, Antonio Carlos Schneider Beck. 1-6 [doi]
- VarSim: A Fast and Accurate Variability and Leakage Aware Thermal SimulatorHameedah Sultan, Smruti R. Sarangi. 1-6 [doi]
- LOFFS: A Low-Overhead File System for Large Flash Memory on Embedded DevicesRunyu Zhang, Duo Liu, Xianzhang Chen, Xiongxiong She, Chaoshu Yang, Yujuan Tan, Zhaoyan Shen, Zili Shao. 1-6 [doi]
- Reuse-trap: Re-purposing Cache Reuse Distance to Defend against Side Channel LeakageHongyu Fang, Milos Doroslovacki, Guru Venkataramani. 1-6 [doi]
- PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse AlgebraBahar Asgari, Ramyad Hadidi, Nima Shoghi Ghaleshahi, Hyesoon Kim. 1-6 [doi]
- EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI SolutionsYuhong Li, Cong Hao, Xiaofan Zhang, Xinheng Liu, Yao Chen, Jinjun Xiong, Wen-mei W. Hwu, Deming Chen. 1-6 [doi]
- Taming Unstructured Sparsity on GPUs via Latency-Aware OptimizationMaohua Zhu, Yuan Xie 0001. 1-6 [doi]
- Reducing DRAM Access Latency via Helper RowsXin Xin, Youtao Zhang, Jun Yang. 1-6 [doi]
- Just Like the Real Thing: Fast Weak Simulation of Quantum ComputationStefan Hillmich, Igor L. Markov, Robert Wille. 1-6 [doi]
- Intermittent Inference with Nonuniformly Compressed Multi-Exit Neural Network for Energy Harvesting Powered DevicesYawen Wu, Zhepeng Wang, Zhenge Jia, Yiyu Shi, Jingtong Hu. 1-6 [doi]
- SAT-Sweeping Enhanced for Logic SynthesisLuca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli. 1-6 [doi]
- On Countermeasures Against the Thermal Covert Channel Attacks Targeting Many-core SystemsHengli Huang, Xiaohang Wang, Yingtao Jiang, Amit Kumar Singh 0002, Mei Yang, Letian Huang. 1-6 [doi]
- INVITED: Computational Methods of Biological ExplorationLouis K. Scheffer. 1-4 [doi]
- Eliminating Redundant Computation in Noisy Quantum Computing SimulationGushu Li, Yufei Ding, Yuan Xie. 1-6 [doi]
- INVITED: New Directions in Distributed Deep Learning: Bringing the Network at Forefront of IoT DesignKartikeya Bhardwaj, Wei Chen, Radu Marculescu. 1-6 [doi]
- Bit-Parallel Vector Composability for Neural AccelerationSoroush Ghodrati, Hardik Sharma, Cliff Young, Nam Sung Kim, Hadi Esmaeilzadeh. 1-6 [doi]
- Wafer Map Defect Patterns Classification using Deep Selective LearningMohamed Baker Alawieh, Duane Boning, David Z. Pan. 1-6 [doi]
- LoPher: SAT-Hardened Logic Embedding on Block CiphersAkashdeep Saha, Sayandeep Saha, Siddhartha Chowdhury, Debdeep Mukhopadhyay, Bhargab B. Bhattacharya. 1-6 [doi]
- Centaur: Hybrid Processing in On/Off-chip Memory Architecture for Graph AnalyticsAbraham Addisie, Valeria Bertacco. 1-6 [doi]
- MEMTONIC: A Neuromorphic Accelerator for Energy Efficient Deep LearningDharanidhar Dang, Sahar Taheri, Bill Lin, Debashis Sahoo. 1-2 [doi]
- Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad StructuresHsiang-Ting Wen, Yu-Jie Cai, Yang Hsu, Yao-Wen Chang. 1-6 [doi]
- Tail: An Automated and Lightweight Gradient Compression Framework for Distributed Deep LearningJinrong Guo, Songlin Hu, Wang Wang, Chunrong Yao, Jizhong Han, Ruixuan Li, Yijun Lu. 1-6 [doi]
- WarningNet: A Deep Learning Platform for Early Warning of Task Failures under Input Perturbation for Reliable Autonomous PlatformsMinah Lee, Burhan Ahmad Mudassar, Taesik Na, Saibal Mukhopadhyay. 1-6 [doi]
- R2D3: A Reliability Engine for 3D Parallel SystemsJavad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski. 1-6 [doi]
- Monitoring the Health of Emerging Neural Network Accelerators with Cost-effective Concurrent TestQi Liu, Tao Liu 0023, Zihao Liu, Wujie Wen, Chengmo Yang. 1-6 [doi]
- TSN-Builder: Enabling Rapid Customization of Resource-Efficient Switches for Time-Sensitive NetworkingJinli Yan, Wei Quan, Xiangrui Yang, Wenwen Fu, Yue Jiang, Hui Yang, ZhiGang Sun. 1-6 [doi]
- Invited: Software Defined Accelerators From Learning Tools EnvironmentAntonino Tumeo, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, Vinay Amatya, David Brooks 0001, Gu-Yeon Wei. 1-6 [doi]
- TYMER: A Yield-based Performance Model for Timing-speculation SRAMShan Shen, Liang Pang, Tianxiang Shao, Ming Ling, Xiao Shi, Longxing Shi. 1-6 [doi]
- Exploiting Computation Reuse for Stencil AcceleratorsYuze Chi, Jason Cong. 1-6 [doi]
- CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource ModelJinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young. 1-6 [doi]
- Realistic Fault Models and Fault Simulation for Quantum Dot Quantum CircuitsCheng-Yun Hsieh, Chen-Hung Wu, Chia-Hsien Huang, His-Sheng Goan, James Chien-Mo Li. 1-6 [doi]
- Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism LevelsDongup Kwon, Suyeon Hur, Hamin Jang, Eriko Nurvitadhi, Jangwoo Kim. 1-6 [doi]
- Late Breaking Results: Reinforcement Learning-based Power Management Policy for Mobile Device SystemsEunji Kwon, Sodam Han, Yoonho Park, Young-Hwan Kim, Seokhyeong Kang. 1-2 [doi]
- CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded SystemsSiva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar 0001. 1-6 [doi]
- INCA: INterruptible CNN Accelerator for Multi-tasking in Embedded RobotsJincheng Yu, Zhilin Xu, Shulin Zeng, Chao Yu, Jiantao Qiu, Chaoyang Shen, Yuanfan Xu, Guohao Dai, Yu Wang 0002, Huazhong Yang. 1-6 [doi]
- SIEVE: Speculative Inference on the Edge with Versatile ExportationBabak Zamirai, Salar Latifi, Pedram Zamirai, Scott A. Mahlke. 1-6 [doi]
- Dadu-CD: Fast and Efficient Processing-in-Memory Accelerator for Collision DetectionYuxin Yang, Xiaoming Chen, Yinhe Han. 1-6 [doi]
- Hardware-Assisted Intellectual Property Protection of Deep Learning ModelsAbhishek Chakraborty 0001, Ankit Mondal, Ankur Srivastava. 1-6 [doi]
- CryptoPIM: In-memory Acceleration for Lattice-based Cryptographic HardwareHamid Nejatollahi, Saransh Gupta, Mohsen Imani, Tajana Simunic Rosing, Rosario Cammarota, Nikil D. Dutt. 1-6 [doi]
- Creating an Agile Hardware Design FlowRick Bahr, Clark W. Barrett, Nikhil Bhagdikar, Alex Carsello, Ross Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng, Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik Kjolstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert, Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen Richardson, Rajsekhar Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell Strange, James J. Thomas, Christopher Torng, Leonard Truong, Nestan Tsiskaridze, Keyi Zhang. 1-6 [doi]
- RedCache: Reduced DRAM CachingPayman Behnam, Mahdi Nazm Bojnordi. 1-6 [doi]
- Convergence-Aware Neural Network TrainingHyungjun Oh, Yongseung Yu, Giha Ryu, Gunjoo Ahn, Yuri Jeong, Yongjun Park, Jiwon Seo. 1-6 [doi]
- Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout SynthesisMingjie Liu, Keren Zhu 0001, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan. 1-6 [doi]
- On the Security of Strong Memristor-based Physically Unclonable FunctionsShaza Zeitouni, Emmanuel Stapf, Hossein Fereidooni, Ahmad-Reza Sadeghi. 1-6 [doi]
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care SetChang Meng, Weikang Qian, Alan Mishchenko. 1-6 [doi]
- Neural Network-Based Side Channel Attacks and CountermeasuresDimitrios Serpanos, Shengqi Yang, Marilyn Wolf. 1-2 [doi]
- Q-CapsNets: A Specialized Framework for Quantizing Capsule NetworksAlberto Marchisio, Beatrice Bussolino, Alessio Colucci, Maurizio Martina, Guido Masera, Muhammad Shafique 0001. 1-6 [doi]
- Learning to Quantize Deep Neural Networks: A Competitive-Collaborative ApproachMd Fahim Faysal Khan, Mohammad Mahdi Kamani, Mehrdad Mahdavi, Vijaykrishnan Narayanan. 1-6 [doi]
- Camouflage: Hardware-assisted CFI for the ARM Linux kernelRémi Denis-Courmont, Hans Liljestrand, Carlos Chinea Perez, Jan-Erik Ekberg. 1-6 [doi]
- Proactive Aging Mitigation in CGRAs through Utilization-Aware AllocationMarcelo Brandalero, Bernardo Neuhaus Lignati, Antonio Carlos Schneider Beck, Muhammad Shafique 0001, Michael Hübner. 1-6 [doi]
- Reducing Bit Writes in Non-volatile Main Memory by Similarity-aware CompressionZhangyu Chen, Yu Hua 0001, Pengfei Zuo, Yuanyuan Sun, Yuncheng Guo. 1-6 [doi]
- Kite: A Family of Heterogeneous Interposer Topologies Enabled via Accurate Interconnect ModelingSrikant Bharadwaj, Jieming Yin, Bradford M. Beckmann, Tushar Krishna. 1-6 [doi]
- Hawkware: Network Intrusion Detection based on Behavior Analysis with ANNs on an IoT DeviceSunwoo Ahn, Hayoon Yi, YoungHan Lee, Whoi Ree Ha, Giyeol Kim, Yunheung Paek. 1-6 [doi]
- Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA SystemsTung-Wei Lin, Wei Chen Tai, Yu-Cheng Lin, Iris Hui-Ru Jiang. 1-6 [doi]
- PETNet: Polycount and Energy Trade-off Deep Networks for Producing 3D Objects from ImagesNitthilan Kanappan Jayakodi, Janardhan Rao Doppa, Partha Pratim Pande. 1-6 [doi]
- In-Memory Computing in Emerging Memory Technologies for Machine Learning: An OverviewKaushik Roy 0001, Indranil Chakraborty, Mustafa Fayez Ali, Aayush Ankit, Amogh Agrawal. 1-6 [doi]
- Verification for Field-coupled Nanocomputing CircuitsMarcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler. 1-6 [doi]
- Late Breaking Results: Automatic Adaptive MOM Capacitor Cell Generation for Analog and Mixed-Signal Layout DesignTzu-Wei Wang, Po-Chang Wu, Mark Po-Hung Lin. 1-2 [doi]
- Reverse-Engineering Deep Neural Networks Using Floating-Point Timing Side-ChannelsCheng Gongye, Yunsi Fei, Thomas Wahl. 1-6 [doi]
- A History-Based Auto-Tuning Framework for Fast and High-Performance DNN Design on GPUJiandong Mu, Mengdi Wang, Lanbo Li, Jun Yang, Wei Lin, Wei Zhang. 1-6 [doi]
- HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical ApplicationsAibin Yan, Xiangfeng Feng, Xiaohu Zhao, Hang Zhou, Jie Cui 0004, Zuobin Ying, Patrick Girard 0001, Xiaoqing Wen. 1-6 [doi]
- The Tao of PAO: Anatomy of a Pin Access Oracle for Detailed RoutingAndrew B. Kahng, Lutong Wang, Bangqi Xu. 1-6 [doi]
- Late Breaking Results: Enabling Containerized Computing and Orchestration of ROS-based Robotic SW Applications on Cloud-Server-Edge ArchitecturesStefano Aldegheri, Nicola Bombieri, Franco Fummi, Simone Girardi, Riccardo Muradore, Nicola Piccinelli. 1-2 [doi]
- Developing Privacy-preserving AI Systems: The Lessons learnedHuili Chen, Siam Umar Hussain, Fabian Boemer, Emmanuel Stapf, Ahmad-Reza Sadeghi, Farinaz Koushanfar, Rosario Cammarota. 1-4 [doi]
- ReTriple: Reduction of Redundant Rendering on Android Devices for Performance and Energy OptimizationsXianfeng Li, Gengchao Li, Xiaole Cui. 1-6 [doi]
- Content Sifting Storage: Achieving Fast Read for Large-scale Image Dataset AnalysisYu Liu, Hong Jiang, Yangtao Wang, Ke Zhou, YiFei Liu, Li Liu. 1-6 [doi]
- Adjoint Transient Sensitivity Analysis for Objective Functions Associated to Many Time PointsWenfei Hu, Zuochang Ye, Yan Wang. 1-6 [doi]
- RELIC-FUN: Logic Identification through Functional Signal ComparisonsJames Geist, Travis Meade, Shaojie Zhang, Yier Jin. 1-6 [doi]
- SCA: A Secure CNN Accelerator for Both Training and InferenceLei Zhao, Youtao Zhang, Jun Yang. 1-6 [doi]
- Tensor Virtualization Technique to Support Efficient Data Reorganization for CNN AcceleratorsDonghyun Kang, Soonhoi Ha. 1-6 [doi]
- Clustering Approach for Solving Traveling Salesman Problems via Ising Model Based SolverAkira Dan, Riu Shimizu, Takeshi Nishikawa, Song Bian, Takashi Sato. 1-6 [doi]
- ReSiPE: ReRAM-based Single-Spiking Processing-In-Memory EngineZiru Li, Bonan Yan, Hai Helen Li. 1-6 [doi]
- CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAMHüsrev Cilasun, Salonik Resch, Zamshed Iqbal Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu. 1-6 [doi]
- Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line AdaptationGouranga Charan, Jubin Hazra, Karsten Beckmann, Xiaocong Du, Gokul Krishnan, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao 0001. 1-6 [doi]
- AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable DevicesMarina Neseem, Jon Nelson, Sherief Reda. 1-6 [doi]
- *Zhifeng Lin, Yanyue Xie, Gang Qian, Sifei Wang, Jun Yu, Jianli Chen. 1-2 [doi]
- DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural NetworksRachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique 0001. 1-6 [doi]
- DDOT: Data Driven Online Tuning for energy efficient accelerationSotirios Xydis, Eleftherios-Iordanis Christoforidis, Dimitrios Soudris. 1-6 [doi]
- Defending Bit-Flip Attack through DNN Weight ReconstructionJingtao Li, Adnan Siraj Rakin, Yan Xiong, Liangliang Chang, Zhezhi He, Deliang Fan, Chaitali Chakrabarti. 1-6 [doi]
- Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural NetworksQilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, YiMao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li. 1-6 [doi]
- NACU: A Non-Linear Arithmetic Unit for Neural NetworksGuido Baccelli, Dimitrios Stathis 0001, Ahmed Hemani, Maurizio Martina. 1-6 [doi]
- Autonomous Warehouse-Scale ComputersSundar Dev, David Lo 0003, Liqun Cheng, Parthasarathy Ranganathan. 1-6 [doi]
- Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-Low Power SoCYijie Wei, Kofi Otseidu, Jie Gu. 1-6 [doi]
- An Efficient Critical Path Generation Algorithm Considering Extensive Path ConstraintsGuannan Guo, Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong. 1-6 [doi]
- Timing-Accurate General-Purpose I/O for Multi- and Many-Core Systems: Scheduling and Hardware SupportShuai Zhao 0004, Zhe Jiang 0004, Xiaotian Dai, Iain Bate, Ibrahim Habli, Wanli Chang 0001. 1-6 [doi]
- A Robust Exponential Integrator Method for Generic Nonlinear Circuit SimulationQuan Chen. 1-6 [doi]
- Multiplicative Complexity of Autosymmetric Functions: Theory and Applications to SecurityAnna Bernasconi 0001, Stelvio Cimato, Valentina Ciriani, Maria Chiara Molteni. 1-6 [doi]
- CAP'NN: Class-Aware Personalized Neural Network InferenceMaedeh Hemmat, Joshua San Miguel, Azadeh Davoodi. 1-6 [doi]
- Flashmark: Watermarking of NOR Flash Memories for Counterfeit DetectionPrawar Poudel, Biswajit Ray, Aleksandar Milenkovic. 1-6 [doi]
- CoExe: An Efficient Co-execution Architecture for Real-Time Neural Network ServicesChubo Liu, Kenli Li 0001, Mingcong Song, Jiechen Zhao, Keqin Li 0001, Tao Li 0006, Zihao Zeng. 1-6 [doi]
- Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning InferenceThierry Tambe, En-Yu Yang, Zishen Wan, Yuntian Deng, Vijay Janapa Reddi, Alexander M. Rush, David Brooks 0001, Gu-Yeon Wei. 1-6 [doi]
- A Novel GPU Overdrive Fault AttackMajid Sabbagh, Yunsi Fei, David R. Kaeli. 1-6 [doi]
- The Power of Simulation for Equivalence Checking in Quantum ComputingLukas Burgholzer, Robert Wille. 1-6 [doi]
- Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCsSumit K. Mandal, Ümit Y. Ogras, Janardhan Rao Doppa, Raid Zuhair Ayoub, Michael Kishinevsky, Partha Pratim Pande. 1-6 [doi]
- CDRing: Reconfigurable Ring Architecture by Exploiting Cycle Decomposition of Torus TopologyLiang Wang, Leibo Liu, Xiaohang Wang, Jie Han 0001, Chenchen Deng, Shaojun Wei. 1-6 [doi]
- Late Breaking Results: Automated Hardware Generation of CNN Models on FPGAsDanielle Tchuinkou Kwadjo, Christophe Bobda. 1-2 [doi]
- BPU: A Blockchain Processing Unit for Accelerated Smart Contract ExecutionTao Lu, Lu Peng. 1-6 [doi]
- An Efficient Deep Learning Accelerator for Compressed Video AnalysisYongchen Wang, Ying Wang 0001, Huawei Li, Yinhe Han, Xiaowei Li 0001. 1-6 [doi]
- TDP-ADMM: A Timing Driven Placement Approach for Superconductive Electronic Circuits Using Alternating Direction Method of MultipliersSoheil Nazar Shahsavani, Massoud Pedram. 1-6 [doi]
- Characterization and Applications of Spatial Variation Models for Silicon Microring-Based Optical TransceiversYuyang Wang, Jared Hulme, Peng Sun, Mudit Jain, M. Ashkan Seyedi, Marco Fiorentino, Raymond G. Beausoleil, Kwang-Ting Cheng. 1-6 [doi]