Abstract is missing.
- The VHDL Validation SuiteJames Armstrong, Chang Cho, Sandeep Shah, Chakravarthy Kosaraju. 2-7 [doi]
- NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/INagisa Ishiura, Hiroto Yasuura, Shuzo Yajima. 8-13 [doi]
- An Intermediate Representation for Behavioral SynthesisNikil D. Dutt, Tedd Hadley, Daniel Gajski. 14-19 [doi]
- Optimization by Simulated Evolution with Applications to Standard Cell PlacementRalph-Michael Kling, Prithviraj Banerjee. 20-25 [doi]
- Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout ProblemsYoussef Saab, Vasant B. Rao. 26-31 [doi]
- Integrated Placement for Mixed Macro Cell and Standard Cell DesignsMichael Upton, Khosrow Samii, Stephen Sugiyama. 32-35 [doi]
- A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated AnnealingAbhijit Chatterjee, Richard I. Hartley. 36-39 [doi]
- Efficient Implementation of a BDD PackageKarl S. Brace, Richard L. Rudell, Randal E. Bryant. 40-45 [doi]
- Sequential Circuit Verification Using Symbolic Model CheckingJerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill. 46-51 [doi]
- Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function ManipulationShin-ichi Minato, Nagisa Ishiura, Shuzo Yajima. 52-57 [doi]
- Women in the Microelectronics Industry (Panel Abstract)Petra Michel. 58
- Relative Scheduling Under Timing ConstraintsDavid C. Ku, Giovanni De Micheli. 59-64 [doi]
- Optimum and Heuristic Data Path Scheduling Under Resource ConstraintsCheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin. 65-70 [doi]
- The Combination of Scheduling, Allocation, and Mapping in a Single AlgorithmRichard J. Cloutier, Donald E. Thomas. 71-76 [doi]
- Timing Driven Placement Using Complete Path DelaysWilm E. Donath, Reini J. Norman, Bhuwan K. Agrawal, Stephen E. Bello, Sang-Yong Han, Jerome M. Kurtzberg, Paul Lowy, Roger I. McMillan. 84-89 [doi]
- An Adaptive Timing-Driven Layout for High Speed VLSISuphachai Sutanthavibul, Eugene Shragowitz. 90-95 [doi]
- A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length ConstraintMasayuki Terai, Kazuhiro Takahashi, Koji Sato. 96-102 [doi]
- Performance-Driven Constructive PlacementIchiang Lin, David Hung-Chang Du. 103-106 [doi]
- MHERTZ: A New Optimization Algorithm for Floorplanning and Global RoutingDaniel R. Brasen, Michael L. Bushnell. 107-110 [doi]
- Analysis and Design of Latch-Controlled Synchronous Digital CircuitsKarem A. Sakallah, Trevor N. Mudge, Kunle Olukotun. 111-117 [doi]
- Timing Verification Using HDTVAlan R. Martello, Steven P. Levitan, Donald M. Chiarulli. 118-123 [doi]
- Timing Analysis in Precharge/Unate NetworksPatrick C. McGeer, Robert K. Brayton. 124-129 [doi]
- Coded Time-Symbolic Simulation Using Shared Binary Decision DiagramNagisa Ishiura, Yutaka Deguchi, Shuzo Yajima. 130-135 [doi]
- Design Management Based on Design TracesAndrea Casotto, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli. 136-141 [doi]
- Meta Data Management in the NELSIS CAD FrameworkPieter van der Wolf, G. W. Sloof, Peter Bingley, Patrick Dewilde. 142-149 [doi]
- An Intelligent Component Database for Behavioral SynthesisGwo-Dong Chen, Daniel Gajski. 150-155 [doi]
- Design Data Management in a CAD Framework EnvironmentLung-Chun Liu. 156-161 [doi]
- Memory, Control and Communications Synthesis for Scheduled AlgorithmsDouglas M. Grant, Peter B. Denyer. 162-167 [doi]
- A Generalized Interconnect Model for Data Path SynthesisTai A. Ly, W. Lloyd Elwood, Emil F. Girczyc. 168-173 [doi]
- Automatic Operator Configuration in the Synthesis of Pipelined ArchitecturesKristen N. McNall, Albert E. Casavant. 174-179 [doi]
- An Optimal Algorithm for Floorplan Area OptimizationTing-Chi Wang, D. F. Wong. 180-186 [doi]
- An Analytical Approach to Floorplan Design and OptimizationSuphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen. 187-192 [doi]
- Pad Placement and Ring Routing for Custom Chip LayoutDeborah C. Wang. 193-199 [doi]
- Comparing Structurally Different Views of a VLSI DesignMike Spreitzer. 200-212 [doi]
- Verification of Interacting Sequential CircuitsAbhijit Ghosh, Srinivas Devadas, A. Richard Newton. 213-219 [doi]
- Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic CircuitsSrinivas Devadas, Kurt Keutzer. 221-227 [doi]
- Is Redundancy Necessary to Reduce DelayKurt Keutzer, Sharad Malik, Alexander Saldanha. 228-234 [doi]
- Test Function Specification in SynthesisVishwani D. Agrawal, Kwang-Ting Cheng. 235-240 [doi]
- Layout Synthesis of MOS Digital CellsAntun Domic. 241-245 [doi]
- A Practical Online Design Rule Checking SystemGoro Suzuki, Yoshio Okamura. 246-252 [doi]
- Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAWErik C. Carlson, Rob A. Rutenbar. 253-259 [doi]
- BREL - a Prolog Knowledge-based System Shell for VLSI CADMarwan A. Jabri. 272-277 [doi]
- Design Methodology Management - a CAD Framework Initiative PerspectiveKenneth W. Fiduk, Sally Kleinfeldt, Marta Kosarchyn, Eileen B. Perez. 278-283 [doi]
- Boolean Resubstitution with Permissible Functions and Binary Decision DiagramsHitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita. 284-289 [doi]
- Reduced Offsets for Two-Level Multi-Valued Logic MinimizationAbdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli. 290-296 [doi]
- The Use of Observability and External Don t Cares for the Simplification of Multi-Level NetworksHamid Savoj, Robert K. Brayton. 297-301 [doi]
- An Entropy Measure for the Complexity of Multi-Output Boolean FunctionsKwang-Ting Cheng, Vishwani D. Agrawal. 302-305 [doi]
- Global Routing Considerations in a Cell Synthesis SystemDwight D. Hill, Don Shugard. 312-316 [doi]
- Benchmarks for Cell SynthesisDwight D. Hill, Bryan Preas. 317-320 [doi]
- New Algorithm for Overlapping Cell Treatment in Hierarchical CAD Data/Electron Beam Exposure Data ConversionTsuneo Okubo, Takashi Watanabe, Kou Wada. 321-326 [doi]
- Design of Repairable and Fully Diagnosable Folded PLAs for Yield EnhancementChin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang. 327-332 [doi]
- NASFLOW, a Simulation Tool for Silicon Technology DevelopmentD. David Forsythe, Atul P. Agarwal, Chune-Sin Yeh, Sheldon Aronowitz, Bhaskar Gadepally. 333-337 [doi]
- Testing Strategies for the 1990 s (Panel Abstract)Alberto L. Sangiovanni-Vincentelli. 338
- Timing Optimization for Multi-Level Combinational NetworksKuang-Chien Chen, Saburo Muroga. 339-344 [doi]
- Logic Optimization Algorithm by Linear Programming ApproachNaohiro Kageyama, Chihei Miura, Tsuguo Shimizu. 345-348 [doi]
- Delay and Area Optimization in Standard-Cell DesignShen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh. 349-352 [doi]
- Algorithms for Library-Specific Sizing of Combinational LogicPak K. Chan. 353-356 [doi]
- A Heuristic Algorithm for the Fanout ProblemKanwar Jit Singh, Alberto L. Sangiovanni-Vincentelli. 357-360 [doi]
- A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-betweenJohn P. Fishburn. 361-364 [doi]
- Multilevel Synthesis Minimizing the Routing FactorPierre Abouzeid, K. Sakouti, Gabriele Saucier, Franck Poirot. 365-368 [doi]
- Layout Compaction with Attractive and Repulsive ConstraintsAkira Onozawa. 369-374 [doi]
- A Hierarchy Preserving Hierarchical CompactorDavid Marple. 375-381 [doi]
- An O(::::n:::::::1.5:::log::::n::::) 1-d Compaction AlgorithmChi-Yuan Lo, Ravi Varadarajan. 382-387 [doi]
- Datapath Generator Based on Gate-Level Symbolic LayoutNobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori. 388-393 [doi]
- Parallel Circuit Simulation Using Hierarchical RelaxationGih-Guang Hung, Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh. 394-399 [doi]
- PARASPICE: A Parallel Circuit Simulator for Shared-Memory MultiprocessorsGung-Chung Yang. 400-405 [doi]
- Waveform Moment Methods for Improved Interconnection AnalysisSteven Paul McCormick, Jonathan Allen. 406-412 [doi]
- System Simulation of Printed Circuit Boards Including Packages and ConnectorsK. Adamiak, R. Allen, J. Poltz, C. Rebizant, A. Wexler. 413-418 [doi]
- A Framework for Industrial Layout GeneratorsWayne Bower, Carl Seaquist, Wayne Wolf. 419-424 [doi]
- Organized C: A Unified Method of Handling Data in CAD Algorithms and DatabasesJiri Soukup. 425-430 [doi]
- An Object-Oriented VHDL Design EnvironmentMoon-Jung Chung, Sangchul Kim. 431-436 [doi]
- An Object-Oriented Kernel for an Integrated Design and Process Planning SystemS. J. Feghhi, Michael M. Marefat, Rangasami L. Kashyap. 437-443 [doi]
- Percolation Based SynthesisRoni Potasman, Joseph Lis, Alexandru Nicolau, Daniel Gajski. 444-449 [doi]
- Synthesis Using Path-Based scheduling: algorithms and ExercisesRaul Compasano, Reinaldo A. Bergamaschi. 450-455 [doi]
- Global Hardware Synthesis from Behavioral Dataflow DescriptionsJosef Scheichenzuber, Werner Grass, Ulrich Lauther, Sabine März. 456-461 [doi]
- A Transistor Reordering Technique for Gate Matrix LayoutUminder Singh, C. Y. Roger Chen. 462-467 [doi]
- PALACE: A Kayout Generator for SCVS Logic BlocksKnut M. Just, Edgar Auer, Werner L. Schiele, Alexander Schwaferts. 468-473 [doi]
- LiB: A Cell Layout GeneratorYung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu. 474-479 [doi]
- Techniques for Unit-Delay Compiled SimulationPeter M. Maurer, Zhicheng Wang. 480-484 [doi]
- Distributed and Parallel Demand Driven Logic SimulationK. Subramanian, Mehdi R. Zargham. 485-490 [doi]
- LECSIM: A Levelized Event Driven Compiled Logic SimulationZhicheng Wang, Peter M. Maurer. 491-496 [doi]
- Standards, Openness and Design Environments in Electronic Design Automation (Panel Abstract)A. Richard Newton. 497-498
- Data Path Allocation Based on Bipartite Weighted MatchingChu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu. 499-504 [doi]
- Data Path Tradeoffs Using MABALKayhan Küçükçakar, Alice C. Parker. 511-516 [doi]
- Symbolic Simulation - Techniques and ApplicationsRandal E. Bryant. 517-521 [doi]
- An Efficient Delay Test Generation System for Combinational Logic CircuitsEun Sei Park, M. Ray Mercer. 522-528 [doi]
- Automatic Incorporation of On-Chip Testability CircuitsNoriyuki Ito. 529-534 [doi]
- Proofs: A Fast, Memory Efficient Sequential Circuit Fault SimulatorThomas M. Niermann, Wu-Tung Cheng, Janak H. Patel. 535-540 [doi]
- Integration of Hardware and Software in Embedded Systems Design (Panel Abstract)William Lattin. 541
- Architecture Synthesis of High-Performance Application-Specific ProcessorsMauricio Breternitz Jr., John Paul Shen. 542-548 [doi]
- High-Level Synthesis: Technology Transfer to IndustryRobin C. Sarma, Mark D. Dooley, N. Craig Newman, Graham Hetherington. 549-554 [doi]
- ASSURE: Automated Design for DependabilityPatrick Edmond, Anurag P. Gupta, Daniel P. Siewiorek, Audrey A. Brennan. 555-560 [doi]
- Constraint Generation for Routing Analog CircuitsUmakanta Choudhury, Alberto L. Sangiovanni-Vincentelli. 561-566 [doi]
- Segmented Channel RoutingJonathan W. Greene, Vwani P. Roychowdhury, Sinan Kaptanoglu, Abbas El Gamal. 567-572 [doi]
- Clock Routing for High-Performance ICsMichael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh. 573-579 [doi]
- Sequential Test Generation at the Register-Transfer and Logic LevelsAbhijit Ghosh, Srinivas Devadas, A. Richard Newton. 580-586 [doi]
- Behavioral Fault Simulation in VHDLP. C. Ward, James R. Armstrong. 587-593 [doi]
- Speed Up of Test Generation Using High-Level PrimitivesRamachandra P. Kunda, Jacob A. Abraham, Bharat Deep Rathi, Prakash Narain. 594-599 [doi]
- Impact and Evaluation of Competing Implementation Media for ASIC s (Panel Abstract)Kurt Keutzer. 600
- A Unified Approach to the Decomposition and Re-Decomposition of Sequential MachinesPranav Ashar, Srinivas Devadas, A. Richard Newton. 601-606 [doi]
- Corolla Based Circuit Partitioning and ResynthesisSujit Dey, Franc Brglez, Gershon Kedem. 607-612 [doi]
- Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate ArraysRobert J. Francis, Jonathan Rose, Kevin Chung. 613-619 [doi]
- Logic Synthesis for Programmable Gate ArraysRajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 620-625 [doi]
- A Gridless Router for Industrial Design RulesWerner L. Schiele, Th. Krüger, Knut M. Just, F. H. Kirsch. 626-631 [doi]
- Layout Optimization by Pattern ModificationRamin Hojati. 632-637 [doi]
- A Channel/Switchbox Definition Algorithm for Building-Block LayoutYang Cai, D. F. Wong. 638-641 [doi]
- New Placement and Global Routing Algorithms for Standard Cell LayoutsMasato Edahiro, Takeshi Yoshimura. 642-645 [doi]
- A Hardware Implementation of Gridless Routing Based on Content Addressable MemoryMasao Sato, Kazuto Kubota, Tatsuo Ohtsuki. 646-649 [doi]
- PHIGURE: A Parallel Hierarchical Global RouterRandall J. Brouwer, Prithviraj Banerjee. 650-653 [doi]
- Automatic Test Generation Using Quadratic 0-1 ProgrammingSrimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell. 654-659 [doi]
- SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational CircuitsHyung Ki Lee, Dong Sam Ha. 660-666 [doi]
- EST: The New Frontier in Automatic Test-Pattern GenerationJohn Giraldi, Michael L. Bushnell. 667-672 [doi]
- The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable DesignKenneth M. Butler, M. Ray Mercer. 673-678 [doi]
- Object Databases in Electronic Design: Implementation Experiences (Panel Abstract)Tim Andrews. 679
- Abstract Data Types and High-Level SynthesisGregory S. Whitcomb, A. Richard Newton. 680-685 [doi]
- Failure Recovery in the MICON SystemAjay J. Daga, William P. Birmingham. 686-691 [doi]
- The FSM Network Model for Behavioral Synthesis of Control-Dominated MachinesWayne Wolf. 692-697 [doi]
- MISER: An Integrated Three Layer Gridless Channel Router and CompactorRoshan A. Gidwani, Naveed A. Sherwani. 698-703 [doi]
- A Multi-Layer Router Utilizing Over-Cell AreasEvagelos Katsadas, Edwin Kinnen. 704-708 [doi]
- General Models and Algorithms for Over-the-Cell Routing in Standard Cell DesignJason Cong, Bryan Preas, C. L. Liu. 709-715 [doi]
- A Parallel Pattern Mixed-Level Fault SimulatorTyh-Song Hwang, Chung-Len Lee, Wen-Zen Shen, Ching Ping Wu. 716-719 [doi]
- Extension of the Critical Path Tracing AlgorithmT. Ramakrishnan, L. Kinney. 720-723 [doi]
- BIST PLAs, Pass or Fail - A Case StudyShambhu J. Upadhyaya, John A. Thodiyil. 724-727 [doi]
- A Variable Observation Time Method for Testing Delay FaultsWeiwei Mao, Michael D. Ciletti. 728-731 [doi]
- A Fault Analysis Method for Synchronous Sequential CircuitsT. Y. Kuo, J. Y. Lee, J. F. Wang. 732-735 [doi]
- On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract)Sreejit Chakravarty. 736-739 [doi]