Nagisa Ishiura - researchr alias

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Viewing Publication 1 - 34 from 34

2021

Full Hardware Implementation of FreeRTOS-Based Real-Time SystemsWakako Nakano, Yukino Shinohara, Nagisa Ishiura. tencon 2021: 435-440 [doi]

2018

Random testing of compilers' performance based on mixed static and dynamic code comparisonKota Kitaura, Nagisa Ishiura. FSE 2018: 38-44 [doi]

Synthesis of Full Hardware Implementation of RTOS-Based SystemsYuuki Oosako, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara. rsp 2018: 1-7 [doi]

Extending equivalence transformation based program generator for random testing of C compilersShogo Takakura, Mitsuyoshi Iwatsuji, Nagisa Ishiura. FSE 2018: 9-15 [doi]

2017

2016

Reverse Engineering from Mainframe Assembly to C Codes in Legacy MigrationDaisuke Fujiwara, Nagisa Ishiura, Ryo Sakai, Ryo Aoki, Takashi Ogawara. iiaiaai 2016: 1058-1063 [doi]

Detecting Arithmetic Optimization Opportunities for C Compilers by Randomly Generated Equivalent ProgramsAtsushi Hashimoto, Nagisa Ishiura. ipsj, 9:21-29, 2016. [doi]

Random testing of C compilers based on test program generation by equivalence transformationKazuhiro Nakamura, Nagisa Ishiura. apccas 2016: 676-679 [doi]

2014

Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of ExpressionsEriko Nagai, Atsushi Hashimoto, Nagisa Ishiura. ipsj, 7:91-100, 2014. [doi]

2010

Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura. ipsj, 3:161-178, 2010. [doi]

Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded ProcessorsTakahiro Kumura, Soichiro Taga, Nagisa Ishiura, Yoshinori Takeuchi, Masaharu Imai. ipsj, 3:207-221, 2010. [doi]

2008

Special Section on VLSI Design and CAD AlgorithmsNagisa Ishiura. ieicet, 91-A(12):3413-3414, 2008. [doi]

High-Level Synthesis of Software Function CallsMasanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori, Hiroyuki Kanbara, Hiroyuki Tomiyama. ieicet, 91-A(12):3556-3558, 2008. [doi]

2002

Datapath oriented codesign method of application specific DSPs using retargetable compilerNagisa Ishiura, Tatsuo Watanabe. apccas 2002: 55-58 [doi]

2000

Thread partitioning method for hardware compiler bachMizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe. aspdac 2000: 303-308 [doi]

1998

Binding and Scheduling Algorithms for Highly Retargetable CompilationMasayuki Yamaguchi, Nagisa Ishiura, Takashi Kambe. aspdac 1998: 93-98

1995

Optimal Scheduling for Conditional Recource SharingAkihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe. iscas 1995: 2297-2300

1994

Fault simulation for multiple faults by Boolean function manipulationNoriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima. tcad, 13(4):531-535, 1994. [doi]

1992

Linear time fault simulation algorithm using a content addressable memoryNagisa Ishiura, Shuzo Yajima. eurodac 1992: 442-445 [doi]

1991

1990

1989

Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic CircuitsNagisa Ishiura, M. Takahashi, Shuzo Yajima. dac 1989: 497-502 [doi]

Semantics of a Hardware Design Language for Japanese StandardizationHiroto Yasuura, Nagisa Ishiura. dac 1989: 836-839 [doi]

1987

High-Speed Logic Simulation on Vector ProcessorsNagisa Ishiura, Hiroto Yasuura, Shuzo Yajima. tcad, 6(3):305-321, 1987. [doi]

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