Table of Contents

• Live Demonstration: Low Power and Real-Time Obstacle Avoidance System with CMOS Image Sensor and Spiking Neural NetworkWei Chi Huang, Chen-Fu Yeh, Po-An Chen, Yu-Chih Tsai, Kea-Tiong Tang. 1 [doi]
• Live Demonstration: A Study on Monitoring Canine Emotional Changes through Heart Rate VariabilityPang-Yen Ko, Shuenn-Yuh Lee. 1 [doi]
• Live Demonstration: Defect Detection in Material Extrusion with Multimodal Large Language ModelGeorge Wu, Chi-Tsun Cheng, Toh Yen Pang. 1 [doi]
• NoC AI Chip Integration for Industrial IoT Fault Diagnosis and Notification SystemHsu-Chi Chen, Pin-Ching Shen, Yen-Chen Yen, Ying-Yu Wang, Kun-Chih Jimmy Chen. 1 [doi]
• The Intermittent Fault Diagnosis of Analog Circuits Based on EMD-CrossFormerChenyi Zhu, Quan Yin, Jigui Miao, Jindian Chen. 1-5 [doi]
• Live Demonstration: Portable Stimulation System for Transcutaneous Auricular Vagus Nerve StimulationZhan-Xian Liao, Yu-Kai Kang, Shuenn-Yuh Lee, Chou-Ching K. Lin. 1 [doi]
• Live Demonstration: AI-Based Arrhythmia Detection with Wearable ECG and Cloud Platform for Dog Health MonitoringBo-An Shi, Shuenn-Yuh Lee. 1 [doi]
• VESTA: A Versatile SNN-Based Transformer Accelerator with Unified PEs for Multiple Computational LayersChing-Yao Chen, Meng-Chieh Chen, Tian-Sheuan Chang. 6-10 [doi]
• A Lightweight Memory Protection Scheme with Criticality-Aware Encryption and Embedded MAC for Secure DNN AcceleratorsYu-Chuan Lin, Kuen-Jong Lee. 11-15 [doi]
• 3D Digital Compute-in-Memory Benchmark with A5 CFET TechnologyMinji Shon, Junmo Lee, Shimeng Yu. 16-19 [doi]
• Low-Power Consumption Inference of ECG Signals Using Differential Logic NetworksChenxi Feng, Xingbo Wang, Terry Tao Ye. 20-24 [doi]
• A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPSIvan Miro Panades, Vincent Lorrain, Lilian Billod, Inna Kucher, Vincent Templier, Sylvain Choisnet, Nermine Ali, Baptiste Rossigneux, Olivier Bichler, Alexandre Valentian. 25-29 [doi]
• DIET-PIM: Dynamic Importance-based Early Termination for Energy-Efficient Processing-in-Memory AcceleratorCheng-Yang Chang, Chi-Tse Huang, An-Yeu Andy Wu. 30-34 [doi]
• Detecting Speech Deepfakes through Improved Speech Features and Cost FunctionsOscal Tzyh-Chiang Chen, Yun-Chia Hsu, Tun-Sheng Yang. 35-39 [doi]
• A Low-Complexity Reconfigurable FFT Processor for Four Data Overlapping ModesLan-Da Van, Yi-Ho Wang, Shen-Jui Huang, Sau-Gee Chen. 40-44 [doi]
• LD-MDCT Quantization Algorithm Optimization and FPGA Realization Using DUTSQ and SFDP TechniquesFanyang Li, Zhanpeng Yuan, Faxiang Wang. 45-49 [doi]
• Proposal and Validation of Annealing-processor-calculation Method Using Error-diffusion Rounded Interaction MatrixDong Cui, Takayuki Kawahara. 50-54 [doi]
• Efficient Implementation of Parallel Annealing Method with Heisenberg ModelKazuma Kanai, Takayuki Kawahara. 55-59 [doi]
• Global Routing Optimization Analysis based on Deep Reinforcement LearningYing-Tzu Chen, Wei-Kai Cheng. 60-63 [doi]
• Enumeration of Genaralized Parallel Counters for Multi-Input Adder Synthesis for FPGAsMugi Noda, Nagisa Ishiura. 64-68 [doi]
• In-Situ Critical-Path Replica for Variation-Aware Low-Power Designs with Timing Margin DetectionJinn-Shyan Wang, Yong-Chin Miu, Chia-Hua Wu. 69-73 [doi]
• An On-chip High-resolution Delay Measurement Scheme for TSVs in 3DICDong-Yi Chen, Cheng-Hong Lee, Kuen-Jong Lee, Nan-Hsin Tseng, Hsin-Wei Hung, Hao-Yu Yang. 74-78 [doi]
• A Transient-Enhanced Dual-Loop Low-Dropout Linear Regulator in 65-nm SOI CMOS With <1-μs Settling Time for 5G ApplicationsRui Wang, Jin Li, Bo Chen, Tao Yuan. 79-82 [doi]
• A Low-Noise Fully-Differential Bandgap Reference for Low-Power High-Precision ADCsTechapon Songthawornpong, Amorn Jiraseree-amornkun, Thaweesak Thantipwan, Woradorn Wattanapanitch. 83-86 [doi]
• A Low-Power Fully-Differential Chopper-Stabilized LNIA in 22nm FD-SOI for MEMS-based Thermopile SensorsVincent Angelo Bogg's G. Roxas, Ralph Maru M. Grande, Maria Sophia C. Ralota, Rafael M. Pangilinan, Arcel G. Leynes, Maria Theresa G. de Leon. 91-94 [doi]
• Machine Learning based Adaptation for CTLE of Serial LinksSujal Reddy Kariveda, Suraj Kumar Prusty, Nijwm Wary. 95-99 [doi]
• Low Noise Low Power Readout Circuit For Capacitance Based MEMS AccelerometersN. Rakesh, R. S. Ashwin Kumar. 100-104 [doi]
• A Wireless Data and Power Transfer-Enabled MCU for Shape-Configurable Chiplet-Based ComputersJunichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai. 105-109 [doi]
• D2D-GPT: Leveraging Incremental Learning GPT for Seamless Design Rule Conversion Across EDA ToolsChao Wang, Yunxiang Zhang, Wangzilu Lu, Jiajie Huang, Qing Zhang 0008, Minghui Yin, Yuhang Zhang 0008, Zhiqiang Li, Yongfu Li 0002. 110-114 [doi]
• A low-hardware-overhead, high-energy-efficiency, and end-to-end CNN-based feature extraction accelerator for mobile visual SLAMZehua Yin, Bingqiang Liu, Jipeng Wang, Zixuan Shen, Guangyao Li, Chao Wang. 115-119 [doi]
• SSPE: A Device-edge SNN Inference Artificial Intelligence Processor in Supporting Smart ComputingZhou Wang 0005, Haochen Du, Jiuren Zhou, Yanqing Xu, Xiaonan Tang, Tianchun Ye 0001, Shaojun Wei, Shushan Qiao, Shouyi Yin. 120-124 [doi]
• A Precision-Scalable Energy-Efficient DNN Accelerator for Robotic GraspingZixiong Feng, Zhongfeng Wang 0001, Wendong Mao. 125-129 [doi]
• A Streaming Transformer Accelerator with Efficient On-Chip NormalizationNing Zhao, Jiayuan Chen, Jingjing Lv, Chenjia Xie, Yuan Du, Li Du. 130-134 [doi]
• Process and Design Considerations for Spin Orbit Torque MRAMZhaohao Wang, Chao Wang, Min Wang, Chenyi Wang, Kaihua Cao, Chenlin Xu, Cong Zhang, Yunpeng Li, Hongxi Liu. 135-139 [doi]
• A 10-bit Two-Stage Pipeline SAR ADC in 55nm CMOS for Compute-in-Memory ApplicationsXiapeng Xu, Yongteng Ma, Xuliang Yu, Fanzi Meng, Wei-Han Yu, Liang Zhao. 140-143 [doi]
• An Automated Design Platform for ReRAM-based DNN Accelerators with Hardware-Software Co-explorationYung-Cheng Lai, Chin-Fu Nien. 144-148 [doi]
• Interactive Analog IC Layout Tool with Real-time Parasitic-aware Automatic Routing AssistanceYu-Tzu Chen, Chin-Fu Nien, Chin Hsia, Chung-Yi Li. 149-153 [doi]
• Optimizing N-Degree Union Problems in Graph Data Processing for Enhancing the Efficiency of Dynamic GraphsYi-Hua Chen, Pin-Jung Chen, Yu-Pei Liang, Yuan-Hao Chang 0001, Wei Kuan Shih. 154-158 [doi]
• Implementing Content-Defined Chunking for Deduplication in Host-Managed SSDsChe-Min Chen, Yi-Chao Shih, Xin Liu, Wei Kuan Shih, Tseng-Yi Chen. 159-163 [doi]
• Enabling a deleted-key-value-aware garbage collection strategy for LSM-tree on OCSSDZih-Cing Pan, Yi-Chao Shih, Xin Liu, Yu-Pei Liang, Yuan-Hao Chang 0001, Wei Kuan Shih. 164-168 [doi]
• A Resource-Efficient Weight Quantization and Mapping Method for Crossbar Arrays in ReRAM-based Computing-in-Memory SystemsMingyuan Ma, Wei Jiang, Juntao Liu, Li Du, Zhongyuan Ma, Yuan Du. 169-173 [doi]
• Design Exploration of In-Situ Error Correction for Multi-Bit Computation-in-Memory CircuitsTing-An Lin, Po-Tsang Huang. 174-178 [doi]
• TPE: Trajectory Path Encoding for Anonymous Routing Algorithm in NoC-based SystemsKun-Chih Jimmy Chen, Ting-En Kao, Li-Heng Ke. 179-182 [doi]
• A 250.3μW Versatile Sound Feature Extractor Using 1024-point FFT 64-ch LogMel Filter in 40nm CMOSAkiho Kawada, Kenji Kobayashi, Jaewon Shin, Rei Sumikawa, Mototsugu Hamada, Atsutake Kosuge. 183-187 [doi]
• A 500MHz, 0.5% THD With 400mVpp Linear Transimpedance Amplifier (TIA) for Analog Optical and In-memory Computing ApplicationsKuanyu Gu, Zhan Ning, Likai Li, Jingjing Lv, Zhong Zhang, Li Du, Yuan Du. 188-192 [doi]
• Towards Safe and Efficient Analog Circuit Design: Active Learning for Feasibility Region ExplorationSezin Kircali Ata, Zhi-Hui Kong, Anusha James, Lile Cai, Kiat Seng Yeo, Khin Mi Mi Aung, Chuan-Sheng Foo, Ashish James. 193-197 [doi]
• CAN Intrusion Detection System Based on Data Augmentation and Improved Bi-LSTMHaihang Zhao, Anyu Cheng, Yi Wang, Shanshan Wang, Hongrong Wang. 198-202 [doi]
• Pragmatic EDA Flow Runtime Prediction with Machine Learning and Automatic Outlier RemovalI-Lun Tseng. 203-207 [doi]
• Radiation-hardened Configuration Registers with SPI Interface Protocol in a 65nm CMOS TechnologyTai-Lai Liu, Chansyun Yang, Yu-Ju Chuang, Herming Chiueh. 212-216 [doi]
• A Radiation-Hardened Serial Peripheral Interface with an ECC-Protected SRAM in a 65nm CMOS TechnologyMing-Hao Chang, Chansyun Yang, Yu-Ju Chuang, Herming Chiueh. 217-220 [doi]
• Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree TechniquesChen-Ho Chen, Chien-Nan Jimmy Liu, Wei-Ting Tu, Tung-Chieh Chen, Iris Hui-Ru Jiang. 221-225 [doi]
• A Lightweight Post-Processing Method for Voltage-Controlled MTJ based True Random Number GeneratorZirui Wang, Renhe Chen, Yu Gu, Albert Lee, Di Wu, Xufeng Kou. 226-230 [doi]
• Flattening Power Waveforms by Hamming Distance Converter for Side-channel AttacksRyoma Katsube, Taiki Nagatomo, Tomoaki Ukezono. 231-235 [doi]
• Standard Cells with Inverted Inputs in 7nm TechnologyTung-Chun Wu, Rung-Bin Lin. 236-240 [doi]
• Sub-Threshold Delay-Locked Loop with Piecewise Linearization and Time-Mode Proportional-Integral LockingWenhao Wu, Fei Yuan 0005, Yushi Zhou. 241-245 [doi]
• An Error Amplifier With Enhanced Slew Rate and Clamp Function Supporting Multi-Mode Control of Four-Switch-Buck-Boost ConverterHaonan Fan, Jiahao Liu, Wangchen Fan, Weifeng Sun, Zhongyuan Fang. 246-250 [doi]
• Analysis of Complex Behaviors on Memristor - Based Bonhöeffer van der Pol OscillatorYukinojo Kotani, Yoko Uwate, Yoshifumi Nishio. 251-255 [doi]
• A Novel Voltage-Controlled Oscillator Linearized by a Resistorless Dynamic-Degeneration TechniqueJinhen Lee, Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang. 256-260 [doi]
• A Stochastic RMS Jitter Monitoring Circuit for Clock Generators using Central Limit TheoremHyeonmin Park, Ahryung Kim, Jeyeon Lee, SeongHwan Cho. 261-264 [doi]
• A 23.9 ppm/°C Bandgap Reference Circuit with Wide Temperature Range Using Subthreshold PVT DetectorTzung-Je Lee, Ruei-Chi Lai, Aleksandr Vasjanov, Vaidotas Barzdenas. 265-268 [doi]
• A CMOS Transimpedance Amplifier Accommodating Wide CPD and Input Bias Range for Chaos LidarHao-Wei Wu, Chung-Yuan Wang, Huan-Jhong Chen, Yi-Cheng Lin, Ping-Hsuan Hsieh, Fan-Yi Lin, Yuan-Hao Huang, Po-Chiun Huang. 269-272 [doi]
• A High-Power Single-Pole-Double-Throw Switch with High Isolation for Millimeter-wave Satellite ApplicationsHao-Yu Luo, Yi-Fan Tsao. 273-276 [doi]
• VCO with 8-shaped Transformer Coupled Transmission-LineSheng-Lyang Jang, Shih-Hsuan Chen, Jiun-Yu Sung, Wen Cheng Lai, Mao-Hsiu Hsu, Miin-Horng Juang. 277-280 [doi]
• Low Power Low Noise and High Sensitivity FSK/OOK Wake-Up ReceiverMing-Hsuan Kuo, Yi-Hsuan Hsia, Kuang-Wei Cheng. 281-285 [doi]
• A Highly-Efficient Power Amplifier for V-band Inter-Satellite Link ApplicationsHao-Yu Luo, Yi-Fan Tsao. 286-289 [doi]
• A 18.8 GHz Noise Circulating VCO With Implicit Noise Filter for Quantum ComputingYan-Ming Chang, Hsiao-Chin Chen, Chun-Hsuan Fan. 290-292 [doi]
• An 80-GHz Phase-Locked Loop for MillimeterWave Application in 40-nm CMOSPei-Hsuan Wang, Yi-Cheng Liu, Yu-Yuan Huang, Wei-Show Hsu, Yu-Li Hsueh, Yuan-Hung Chung, Tsung-Hsien Lin. 293-296 [doi]
• The Flight Motion Measurement of Yamawaki on Horizontal BarShiela Cabahug, Chia-Cheng Hsieh, Yi-Wei Wang, Ti-Wei Hsu, Yuan-Hsiang Lin. 297-300 [doi]
• Optimizing Computational Efficiency: A Novel Approach through XOR-logic Operation in In-Memory ComputingZheng-Lin Chen, Chao-Ting Huang, Bo-Ruei Huang, Yu-Feng Lin, Ting-Yu Lin, Kun-Lin Tsai, Chi-Chia Sun. 301-305 [doi]
• FPGA-Based Batik Classification Using Quantization Aware Training of MobileNet and Data-flow ImplementationNovendra Setyawan, Chi-Chia Sun, Wen-Kai Kuo, Mao-Hsiu Hsu. 306-310 [doi]
• RUBY - A versatile and customizable social robotAndreas Kitzig, Edwin Naroska, Shanq-Jang Ruan, Marcus Weberskirch, Sinan Yavuz. 311-315 [doi]
• Integrated All-GaN Driver for Non-isolated Resonant ConvertersJianchan Yang, Chin Hsia, Deng-Fong Lu. 316-319 [doi]
• The Light-Weighted Road Fault Identification for Embedded Hardware Platform Using YOLOJunita Sari, Ting Yue, Liang Chang. 320-324 [doi]
• Insect Classification Using Spatial Pyramid Pooling and Convolution Neural NetworkChang-yu Wu, Song-Min Ke, Hoh-Siang Liao, Chen-Hua Chen, Ying-Hsiu Hung, Shin-Chi Lai. 325-329 [doi]
• 2 Resolution FoM in 28-nm CMOSChenyang Han, Yujun Shu, Tianwei Li, Jiangfeng Wu, Yongzhen Chen. 330-334 [doi]
• A Switched-Capacitor Cross-Correlation-Based Time-of-Flight Design for Pulsed Chaos Lidar SystemsYung-Han Tseng, Yi-Cheng Lin, Sheng-Che Lin, Ping-Hsuan Hsieh, Cheng-Ting Lee, Chih-Hao Chang, Fan-Yi Lin. 335-338 [doi]
• Design of Hermite Polynomial Graph Filter and Its Application to Sensor Network Data DenoisingChien-Cheng Tseng, Su-Ling Lee. 339-343 [doi]
• Miniaturized Laser Diode Driver and Microwave Source for Transportable Quantum SensorsZheyi Li, SinNyoung Kim, Reza Tavakoli Dinani, Yijing Zhang, Ilker Eryilmaz, Laurent Berti, Milos Nesladek. 344-348 [doi]
• Automated Optimization for FPGA-Based Sonar Object Recognition SystemsPin-Hao Tung, Geng-Shi Jeng, Bo-Cheng Lai, Yu-Xiang Hung. 349-353 [doi]
• An Eight-Channel Analog Front-End Circuitry for the Application of Neural Signal SensingZu-Jia Lo, Yi-Wei Peng, Ming-Hsuan Tsai, Sheng-Yu Peng. 354-357 [doi]
• Optimizing GPU Data Center PowerTawfik Rahal-Arabi, Paul van der Arend, Ashish Jain, Mehdi Saidi, Rashad Oreifej, Sriram Sundaram, Srilatha Manne, Indrani Paul, Rajit Seahra, Frank Helms, Esha Choukse, Nithish Mahalingam, Brijesh Warrier, Ricardo Bianchini. 358-362 [doi]
• Biobjective Optimization Problems in a Simplified Model of Boost Converter with Photovoltaic InputRyunosuke Numata, Toshimichi Saito. 363-367 [doi]
• Experimental evaluation of an integrated traction inverter used on an electric vehicle platformChih-Chiang Wu, Pan-Hsiang Hsieh, Shin-Hung Chang. 368-371 [doi]
• Model-Based Design Methodology for Non-Inverting Buck-Boost Converter with Enhanced Duty Overlap Control and DVSShang-Chih Yin, Po-Ju Chen, Shang-Chien Yang, Chien-Hung Tsai. 372-376 [doi]
• A Comparative Analysis of SiC MOSFET Performance in a Traction InverterChih-Chiang Wu, Uma Sankar Rout, Yu-Long Wang, Yi-Ling Lin, Jwu-Sheng Hu. 377-381 [doi]
• Multiple-Loop Analysis and Design for Fast-Transient Capacitor-less LDO with Dual-Path Compensation and Zero-Pole placement in 65-nm CMOSPeijuan Ju, Qisong Wu, Dixian Zhao. 382-386 [doi]
• An Incremental Zoom ADC With Quantization Level Shifting Technique For Over-Ranging ReductionHuayue Song, Lei Qian, Guangzu He, Yongfu Li, Yan Liu. 387-391 [doi]
• A Micro-phase Difference Measurement Circuit Using 4-bit Input StageYuki Sasaki, Takuro Noguchi, Yohei Ishikawa, Sumio Fukai, Akio Shimizu. 392-396 [doi]
• A 91.7-dB SNDR Discrete-Time Zoom ADC with a 20-kHz BW in 180-nm CMOSZi-Chi Lin, Chun-Yang Chiu, Yung-Hui Chung. 397-400 [doi]
• A 4 Bit Segmented Current-Steering Harmonic-Cancelling Digital-to-Analog Converter for High Frequency Sine-Wave SynthesisMaximilian Scherzer, Mario Auer. 401-405 [doi]
• A Second-Order Noise Shaping SAR ADC with Fully Passive Integrators and Pole OptimizationChia-Wei Liu, Yi-Ting Hsieh 0001, Shuenn-Yuh Lee, Ju-Yi Chen. 406-409 [doi]
• Method for Measuring Silicon Quantum Dots with TMR SensorSeiji Komatsu, Takayuki Kawahara. 410-413 [doi]
• An ANN-Physical Hybrid GaN HEMT Model for 5G Power AmplifiersZhongzhiguang Lu, Hanchao Li, Yihao Zhuang, Hanlin Xie, Geok Ing Ng, Yuanjin Zheng. 414-418 [doi]
• 2-16 GHz Phase Shifter With Continuous 435° Phase-Control in 130 nm CMOSZiJie Hu, Yongfu Li 0002, Koen Mouthaan. 419-423 [doi]
• A flexible multi-standard I/O interface for chip-to-chip links in 65 nm CMOSJoscha Ilmberger, Niels Fiedler, Andreas Grübl, Johannes Schemmel. 424-427 [doi]
• A Mm-Wave 5G Broadband Power Amplifier with Subthreshold Adaptive Biasing Network in 22 nm FD-SOI CMOSLiang-Wei Ouyang, Clint Sweeney, Jill C. Mayeda, Donald Y. C. Lie, Jerry Lopez. 428-431 [doi]
• A 62nW, 920MHz Wake-up Receiver with Automatic Offset Calibration TechniqueYao-Wei Huang, Yu-Te Liao. 432-436 [doi]
• Digital Baseband Architecture and Simulated Low-IF FSK Receiver PerformanceBrandon P. Hippe, David C. Burnett. 437-441 [doi]
• Toward Structurally Safe Design-for-Trust TechniquesArmin Darjani, Nima Kavand, Akash Kumar 0001. 442-446 [doi]
• PUF-based Lightweight Authentication for Binarized Neural NetworksGokulnath Rajendran, Suman Deb, Anupam Chattopadhyay. 447-451 [doi]
• FHEDGE: Encrypted Inference on Lightweight Edge DevicesSoumik Sinha, Sayandeep Saha, Ayantika Chatterjee, Debdeep Mukhopadhyay. 452-456 [doi]
• Innovations in Hardware Security: Leveraging FeFET Technology for Future OpportunitiesAnirban Kar, Yogesh Singh Chauhan, Hussam Amrouch. 457-460 [doi]
• Robust and Energy-efficient Hardware Architectures for DIZY Stream CipherMartin Schmid, Tolga Arul, Elif Bilge Kavun, Francesco Regazzoni 0001, Orhun Kara. 461-465 [doi]
• Safeguarding the Silicon: Strategies for Integrated Circuit Layout ProtectionJitendra Bhandari, Jayanth Gopinath, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri. 466-470 [doi]
• Computation Complexity Reduction Based on Quick Leaky-Integrate-And-Fire Mechanism for SNNsXinyu Kang, Silong Li, Xingbo Wang, Zhiyuan Xu, Yuru Li, Terry Tao Ye. 471-474 [doi]
• Enhancing Finite State Machine Design Automation with Large Language Models and Prompt Engineering TechniquesQun-Kai Lin, Cheng Hsu, Tian-Sheuan Chang. 475-478 [doi]
• Predicting Beam Switching Directions in Ultra Wideband Spiral Antennas Using Machine Learning AlgorithmsOratai Nikornpon, Pichaya Chaipanya. 479-483 [doi]
• Wide-band Circular Slot Antenna Beam Switching Directions Using Machine Learning AlgorithmsWorakan Noimi, Pichaya Chaipanya. 484-488 [doi]
• Analog Neuron as Generalised Similarity MetricAkhila Remanan, Vineeta Vasudevan Nair, Sruthi Pallathuvalappil, Alex Pappachen James. 489-493 [doi]
• Japanese Vowel-mora Visualization for Dysarthria Rehabilitation with Variational AutoencoderRyuhei Michizoe, Hiroko Kinosada, Hiroki Nishikawa, Ittetsu Taniguchi, Kazuhide Matsunaga, Narikazu Uzawa, Takao Onoye. 494-498 [doi]
• A Multi-Channel Decoupling Method for Feedforward Active Noise Control Using Neural NetworksQinxuan Xiang, Guangzheng Yu, Yijing Chu, Ming Wu 0005, Yuezhe Zhao. 499-503 [doi]
• Design of Extended RISC-V for Q-Learning Hardware Accelerator using HW/SW Co-DesignInfall Syafalni, Muhammad Sulthan Mazaya, Muhammad Raihan Elfazri, Eko Mursito Budi, Nana Sutisna, Rahmat Mulyawan, Trio Adiono, Makoto Ikeda. 504-508 [doi]
• A Dynamic Approximation Processor Based on Out-of-Order RISC-V in 28-nm CMOSTomohiro Yoshita, Junichiro Kadomoto, Hidetsugu Irie. 509-513 [doi]
• LEAM: A Low-Area and Efficient Accelerator of Matrix-Vector Multiplication for Homomorphic EncryptionZhao Cui, Jing Tian. 514-518 [doi]
• The VLSI Architecture Design of a Configurable and High-Throughput Singular Value Decomposition ProcessorTien-Min Chang, Chung-An Shen. 519-523 [doi]
• TG-in-DRAM: A Transmission Gate based Full Adder using Multi-row Activation for enhanced Throughput in CIM ArchitecturesSambhav Sharma, Garima Choudhary, Neha Gupta, Sunil Rathore, Anand Bulusu, Sudeb Dasgupta. 524-528 [doi]
• Physical Design of RISC-V based System-on-Chip using OpenLaneMuhammad Izzatul Fauzan Hasibuan, Raihan Fadhil Yanuarsyah, Muhammad Hanif Hibatullah, Radithya Arisaputra, Infall Syafalni, Nana Sutisna, Trio Adiono, Makoto Ikeda. 529-533 [doi]
• TRNG Based on Multiple Entropy Sources Using CTDSMApurv Pandey, Naveen Kadayinti. 534-538 [doi]
• Design of Novel Systolic Array based NTT for CRYSTALS-Kyber schemeKeerthija Puli, Vikramkumar Pudi. 539-543 [doi]
• Reference-Free Dual-Mode Cell-to-Cell Sensing for Area-Efficient Resistive MemoryByung-Kwon An, Tony Tae-Hyoung Kim. 544-548 [doi]
• A 0.9 V Adaptive Sampling Rate Differential Level Crossing-SAR ADC for Biomedical Signal Acquisition SystemJui-Ting Lin, Yi Hsin Liao, Meysam Akbari, Kea-Tiong Tang. 549-553 [doi]
• A Hybrid Voltage-Time Dual-Slope Capacitance-to-Digital Converter With Noise Shaping for Extracellular Vesicle Sensing SystemsBo-Xun Hong, Tsung-Heng Tsai. 554-557 [doi]
• Charge-Pump-Circuit Implementation for Increasing Sink Current in Low-Volage CMOS Retinal-Prosthesis ChipsWisaroot Sriitsaranusorn, Yuki Nakanishi, Takaya Hattori, Kuang-Chih Tso, Kenzo Shodo, Hironari Takehara, Yoshinori Sunaga, Makito Haruta, Hiroyuki Tashiro, Yasuo Terasawa, Jun Ohta, Kiyotaka Sasagawa. 558-561 [doi]
• A High-voltage Tolerant and Current-accurate Neural Stimulator Based on A Low-voltage CMOS ProcessZeyu Lu, Weijian Chen, Xu Liu. 562-565 [doi]
• A 32-bit Two-step Incremental-ADC with 125.6 dB Dynamic-range for Non-invasive BCI ApplicationsZhenghang Gao, Shiwei Wang, Mingyi Chen. 566-570 [doi]
• An Energy-Efficient and High-Accuracy Spiking Neural Network Utilizing Asynchronous CORDIC for On-FPGA STDP LearningShirui Sheng, Kwen-Siong Chong, Jun-Sheng Ng, Zhiping Lin 0001, Joseph S. Chang, Bah-Hwee Gwee. 571-575 [doi]
• A Readily Driven Zoom ADC with Least-Significant Bit First Quantization for Brain-Computer InterfaceYifan Chen, Guangzu He, Lei Qian, Yongfu Li, Yan Liu. 576-580 [doi]
• A Portable Electrical Stimulation System with User Interface for Multiple tVNS TreatmentZhan-Xian Liao, Yu-Kai Kang, Shuenn-Yuh Lee, Chou-Ching K. Lin. 581-584 [doi]
• Low-power and Small-area Transimpedance Amplifier with Active Inductor in 65 nm CMOSTakato Masuda, Yasuhiro Takahashi. 585-589 [doi]
• A 12 dBm, 0.1-12 GHz Compact Power Mixer based Ultra-Wideband TransmitterPriyadharshini Prabaharan, Sankaran Aniruddhan. 590-594 [doi]
• A Design of PUF Circuit Using Adiabatic LogicShoya Nagata, Yasuhiro Takahashi. 595-598 [doi]
• Design of Low-Power 6T Adiabatic PUF CircuitJiaming Liu, Yasuhiro Takahashi. 599-603 [doi]
• A 1.3 nW, 0.014 %/V and Dual-output CMOS Voltage Reference with Self-biased Current SourceYanshen Luo, Jingci Yang, Yongfu Li, Yanhan Zeng. 604-608 [doi]
• A 348-nW, 10.5-bit Analog Front End with Amplifier Resistor Series Loop for Acoustic ApplicationZihong He, Huiwen Shi, Yongfu Li, Yanhan Zeng. 609-613 [doi]
• ARIELLE: AR-based Independent and Experiential Language Learner on the EdgeJuncheng Man, Lin Shang Hong, Ellia Tio Shu Yi, Rajesh C. Panicker. 614-617 [doi]
• A Novel Prediction Technique for Intermittent UWB Positioning System Using Hybrid LSTM-TrilaterationGotawa Aryo Prakoso, Infall Syafalni, Nana Sutisna, Rahmat Mulyawan, Nur Ahmadi, Trio Adiono, Fakhrul Zaman Rokhani. 618-622 [doi]
• Real-Time Estimation of Respiratory Rate Using Contactless FMCW Radar with Adaptive Filtering for Various Breathing PatternsAdeline Kartika Tiku Putri, Muhammad Heronan Hyanda, Nur Ahmadi, Trio Adiono. 626-630 [doi]
• Cognitive Frailty Classification Models for Older Adults in a Point-of-Care SystemLei Cao, Yang Wei Lim, Maw Pin Tan, Fakhrul Zaman Rokhani. 631-635 [doi]
• GPU-based Ising Machine for Solving Combinatorial Optimization Problems with Enhanced Parallel Tempering TechniquesKuei-Po Huang, Chin-Fu Nien, Yun-Ting Zhang, Cheng-Kuang Lee, Yu-Cheng Wang. 636-640 [doi]
• OCR is All you need: Importing Multi-Modality into Image-based Defect Classification SystemChih-Chung Hsu, Chia-Ming Lee, Po-Tsun Yu, Chun-Hung Sun, Kuang-Ming Wu. 641-645 [doi]
• Low-Complexity RDFT-Based Impedance Calculation for Enhanced EIS AnalysisWen-Ho Juang, Li-Chuan Hsu, Hau-Ping Chen, En-Chi Yang, Ming-Hwa Sheu. 646-648 [doi]
• Op-Amp sizing with large number of design variables using TuRBOTsuyoshi Masubuchi, Nobukazu Takai. 649-653 [doi]
• Scaling NVMs in Event-Driven Architectures for Edge InferenceJunren Chen, Kanishkan Vadivel, Dawit Burusie Abdi, Priya Venugopal, Refik Bilgic, Giacomo Indiveri, Fernando García-Redondo, Dwaipayan Biswas. 654-658 [doi]
• COLEA: A Low-light Enhancement Accelerator with Memory-usage Reducing StrategyJunhao Zhang, Liang Chang. 659-663 [doi]
• A 28nm 64.5TOPS/W Sparse Transformer Accelerator with Partial Product-based Speculation and Sparsity-Adaptive ComputationMing-Guang Lin, Jiing-Ping Wang, Yuan-June Luo, An-Yeu Andy Wu. 664-668 [doi]
• Memory-Oriented Structural Pruning for Anomalous Sound Detection System on MicrocontrollersChieh-Wen Yang, Yi-Cheng Lo, Tsung-Lin Tsai, An-Yeu Andy Wu. 669-673 [doi]
• Quantized Optical Neural Network Based on Microring Resonators with On-Chip ModulationYun Hu, Huifan Zhang, Pingqiang Zhou. 674-678 [doi]
• An Efficient On-Chip Storage Solution for CNN Accelerator Based on Self-tuning and Co-schedulingChengrui Li, Ning Zhao, Xiaopeng Zhang, Wei Gao, Chenjia Xie, Yuan Du, Li Du. 679-682 [doi]
• A Novel Standard Cell Layout Methodology for Low Power IOT ApplicationsAnuj Bhardwaj, Anand Mishra, Rohit Kumar Gupta. 683-686 [doi]
• Design and Implementation of Doppler Centroid Estimation with Quality Index for Real-Time SAR ImagingPo-Ta Chen, Pei-Yun Tsai 0001, Sz-Yuan Lee. 687-691 [doi]
• Engineering ASAP7 PDK with Buried Power Rail and Backside Metal TechnologiesWen-cheng Yang, Ting-An Jian, Yu-Cheng Lin, Rung-Bin Lin. 692-696 [doi]
• Random Clock Gating for Side-channel ProtectionYui Koyanagi, Tomoaki Ukezono. 697-701 [doi]
• GRS: A General RISC-V SIMD Vector Acceleration Processor for Artificial Intelligence ApplicationsZhou Wang 0005, Haochen Du, Jiuren Zhou, Yang Zhou, Xiaonan Tang, Tianchun Ye 0001, Shaojun Wei, Shushan Qiao, Shouyi Yin. 702-706 [doi]
• An improved method for a set-pair routing problem by SATKoki Nagakura, Kunihiro Fujiyoshi. 707-711 [doi]
• A 14.6-ENOB Second-Order Noise-Shaping SAR ADC With kT/C Noise ShiftingYiyao Huang, Guolong Fu, Xianghui Zhang, Yanbo Zhang, Shubin Liu, Zhangming Zhu. 712-716 [doi]
• A 14b Calibration-Free Pipelined SAR ADC Using a Single-Stage Gain Boost FIAHaoyu Tian, Guolong Fu, Yuzhou Xiong, Yanbo Zhang, Shubin Liu, Zhangming Zhu. 717-721 [doi]
• A 10-MS/s Binary Weight-merged SAR ADC for Real-Time Health-Monitoring System ApplicationsYu-wei Chang, Ming-Yueh Ku, Shuenn-Yuh Lee, Ju-Yi Chen. 722-725 [doi]
• Design of a Low-Power LNIA-ADC Interface Circuit in 22nm FDSOI for a Thermopile Sensor in Biomedical ApplicationJeremy David Molines, Zylm Sabater, Fergie John Frange, Eugene Imbang, Vincent Angelo Bogg's G. Roxas, Maria Sophia Ralota, Arcel G. Leynes, Rafael M. Pangilinan, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon. 731-735 [doi]
• A High Gain Range Low Gain Step dB-Linear Programmable Gain Amplifier with Parallel Complementary Switching Current MethodTzung-Je Lee, Chien-Hsiang Chao. 736-739 [doi]
• Design of a 3rd-Order 12-bit Incremental ADC for Power Monitoring ApplicationsChia-Min Lai, Chung-Chih Hung. 740-743 [doi]
• Active Gate Driver Design Using Differential Timing-based Miller Detector for Power MOSFETPradyumna Vellanki, Venkata Naveen Kolakaluri, Yun-Che Chang, L. S. S. Pavan Kumar Chodisetti, Mitch Ming-Chi Chou, Chua-Chin Wang. 744-748 [doi]
• A 88.6%-Efficient Multi-Input Capacitive-Based Energy Combiner with Adaptive Path Control for WSN-IoT ApplicationsTrisha Isobelle V. Arboleda, Klenn Louie P. Laure, Mike Martin C. Diangco, Jefferson A. Hora, Xi Zhu 0001. 749-753 [doi]
• Triple-Band RF Energy Harvesting System Using TDM Combiner Drawing 1.5 μW in 22nm FDSOI TechnologyMike Martin C. Diangco, Jefferson A. Hora, Xi Zhu 0001. 754-758 [doi]
• Time Domain Analysis of WPT System with Parallel Resonant Secondary Stage Driving Rectifier LoadWing-Hung Ki, Yuan Yao, Chi-Ying Tsui. 759-762 [doi]
• Methods of Reducing the Intrinsic Loss for Continuously-Scalable-Conversion-Ratio SC ConvertersYongjuan Shi, Chen Hu, Xiaosen Liu, Xun Liu, Junmin Jiang. 763-766 [doi]
• An AOT-COT Dual-Mode Three-Level Buck Converter With Wide Load and Input RangesZhiming He, Yan Lu. 767-771 [doi]
• A Current-Mode Electrical Stimulator with Charge Balance for Neural Stimulation ApplicationsYueh-En Huang, Sheng-Yu Peng. 772-775 [doi]
• Efficient Polynomial Arithmetic and Hash Modules for ML-DSA and ML-KEM StandardsQuang Dang Truong, Hanho Lee. 776-780 [doi]
• Lightweight Binary Neural Networks for Edge DevicesHyunkyu Kang, Seokhoon Kim, Sanghyeok Moon, Youngmin Kim. 781-784 [doi]
• Memristor crossbar circuits of unconventional computing for low-power IoT devicesRina Yoon, Seokjin Oh, Seungmyeong Cho, Ilpyeong Yoon, Jihwan Mun, Kyeong-Sik Min. 785-789 [doi]
• An Efficient Sparse CNN Architecture with Index-based Kernel TransformationPo-Ting Chen, Shan-Chi Yu, Ing-Chao Lin. 790-794 [doi]
• TNSS: Two-Nibble Sparsity-Aware Stride-Decomposing Acceleration for Convolutional Neural NetworksYun-Yin Huang, Yu-Guang Chen, Jing-Yang Jou. 795-799 [doi]
• Secure Control Logic Design for Dual Key Logic LockingYi-Chen Chen, Shih-Hsu Huang. 800-803 [doi]
• Live Demonstration: A Soft Mist Inhaler with Sound and Motion Sensors for Improving Drug Usage EfficiencyMou-Wei Chang, Chun-Wei Chiu, Fang-Hao Hsiao, Hsuan-Yu Chen, Wen-Jui Wu, Yu-Te Liao. 804 [doi]
• Live Demonstration: An AIoT Wearable ECG Patch with Cloud Platform for Cardiac Disease DetectionMing-Yueh Ku, Yi-Ting Hsieh 0001, Jia-Jun Liu, Ju-Yi Chen, Shuenn-Yuh Lee. 805 [doi]
• Live Demonstration: A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPSIvan Miro Panades, Vincent Lorrain, Lilian Billod, Inna Kucher, Vincent Templier, Sylvain Choisnet, Nermine Ali, Baptiste Rossigneux, Olivier Bichler, Alexandre Valentian. 810 [doi]
• Live Demonstration: Low Cost AES-256 Circuit Design and ApplicationChia-Chou Chuang, Yu-Lun Jheng, Chien Huang, Lu-Ying Huang, Pei-Yin Chen, Narn-Yih Lee. 811 [doi]