Table of Contents

• Image enhancement using DCT-based matrix homomorphic filtering methodSu-Ling Lee, Chien-Cheng Tseng. 1-4 [doi]
• Optimized three scores combination for image quality assessmentKei Ishiyama, Yosuke Sugiura, Tetsuya Shimamura. 5-8 [doi]
• Accelerating residue-to-binary conversion of very high cardinality moduli set for fully homomorphic encryptionTruong Phu Truan Ho, Chip-Hong Chang. 9-12 [doi]
• An ultra-low-power variable-accuracy bit-serial FFT butterfly processing element for IoT sensorsYue Lu, Tom J. Kazmierski. 13-16 [doi]
• Lower-norm criterion based background noise estimation for simple observation modelAkitoshi Itai, Yuta Hara. 17-20 [doi]
• Binaural-cue-based noise reduction using multirate quasi-ANSI filter bank for hearing aidsHuei-Shiuan Tang, Cheng-Yen Yang, Chih-Wei Liu, Chia-Cheng Chien. 21-24 [doi]
• A digital LDO with transient enhancement and limit cycle oscillation reductionMo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins. 25-28 [doi]
• A sub-1V low dropout regulator with improved transient performance for low power digital systemsY. S. Jiang, D. Wang, P. K. Chan. 29-32 [doi]
• Digitally assisted low dropout regulator design for low duty cycle IoT applicationsYan Lu. 33-36 [doi]
• A digital low-dropout-regulator with steady-state load current (SLC) estimator and dynamic gain scaling (DGS) controlJian-He Lin, Wen-Jie Tsou, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Lsung-Yen Lsai. 37-40 [doi]
• A comparative analysis on binary and multiple-unary weighted power stage design for digital LDOFan Yang, Yasu Lu, Philip K. T. Mok. 41-42 [doi]
• Embedded hybrid LDO topologies for digital load circuitsSaad Bin Nasir, Arijit Raychowdhury. 43-46 [doi]
• A low-power LDO circuit with a fast load regulationYoung Jae Jang, Seong Eun Cho, Byungsub Kim, Jae-Yoon Sim, Hong June Park. 47-49 [doi]
• Mobility patterns of human population among university campusesShu-Min Zhang, Xiang Li. 50-53 [doi]
• Improving robustness of power systems via optimal link switch-offHaicheng Tu, Yongxiang Xia, Herbert H. C. Iu, Chi K. Tse. 54-56 [doi]
• An effective rewiring strategy for optimizing traffic performance of communication networksZhenhao Chen, Jiajing Wu, Zibin Zheng. 57-60 [doi]
• Effect of traffic generation patterns on traffic performance of complex networksJunwen Zeng, Jiajing Wu, Zhenhao Chen, Zibin Zheng. 61-64 [doi]
• Chaos propagation in coupled chaotic circuits with multi-ring combinationTakahiro Chikazawa, Yoko Uwate, Yoshifumi Nishio. 65-68 [doi]
• Synchronization in complex networks by coupled parametrically excited oscillators with parameter mismatchKosuke Oi, Yoko Uwate, Yoshifumi Nishio. 69-72 [doi]
• A 1V low-power CMOS resistance-to-frequency converter using hybrid transconductor for IoTKuan Chuang Koay, Pak Kwong Chan. 73-76 [doi]
• A high output-swing current mirror with neuron MOSFETs in standard CMOS technologyAkio Shimizu, Yohei Ishikawa, Sumio Fukai. 77-78 [doi]
• Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switchSarang Kazeminia, Arefeh Soltani. 79-82 [doi]
• Analog integrated audio frequency synthesizerDouglas Andersson Hagglund, Girish Aramanekoppa Subbarao, Mohammed Abdulaziz, Markus Törmänen. 83-86 [doi]
• A self biased full range current sensor for buck regulatorChundong Wu, Wang Ling Goh, Wei Mao, Lei Wang, Yat-Hei Lam, Alan Chang, Yong Lian. 87-90 [doi]
• A CMOS sinusoidal signal generator based on mixed-time processing for electrical bioimpedance spectroscopy supporting beta dispersion rangeSoon-Jae Kweon, Sung-Hun Jo, Jeong-Ho Park, Hyung-Joun Yoo. 91-94 [doi]
• A single on/off reference tracking buck converter using turning point prediction for DVFS applicationSijie Pan, Philip K. T. Mok. 95-98 [doi]
• A fast transient LDO based on dual loop FVF with high PSRRLei Wang, Wei Mao, Chundong Wu, Alan Chang, Yong Lian. 99-102 [doi]
• A 0.6-V power efficient digital LDO with 99.7% current efficiency utilizing load current aware clock modulation for fast transient responseKarthik Gopal Jayaraman, Karim Rawy, Tony T. Kim. 103-106 [doi]
• RF energy harvester with peak power conversion efficiency trackingMenghan Sun, Damith Chinthana Ranasinghe, Said F. Al-Sarawi. 107-110 [doi]
• A compact, resource sharing on-chip soft-start technique for automotive DC-DC convertersK. T. Hafeez, Ashudeb Dutta, Shiv Govind Singh, Krishna Kanth Gowri Avalur. 111-114 [doi]
• Success rate model for fully AES-128 in correlation power analysisAli Akbar Pammu, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Nan Liu, Bah-Hwee Gwee. 115-118 [doi]
• Compact spin transfer torque non-volatile flip flop design for power-gating architectureKarim Ali, Fei Li, Sunny Y. H. Lua, Chun-Huat Heng. 119-122 [doi]
• A low power and compact physical unclonable function based on the cascode current mirrorsShibang Lin, Dejian Liang, Yuan Cao, Xiaofang Pan, Xiaojin Zhao. 127-130 [doi]
• CMOS-memristor dendrite threshold circuitsAskhat Zhanbossinov, Kamilya Smagulova, Alex Pappachen James. 131-134 [doi]
• Lateral silicon nanowire based standard cell design for higher performanceOm. Prakash, M. Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas, Satish Maheshwaram. 135-138 [doi]
• An FPGA-based quality filter for de novo sequence assembly pipelineChun-Shen Liu, Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu. 139-142 [doi]
• MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imagingShin-Shiang Wang, Yi-Chi Tien, Yin-Tsung Hwang, Jin-Fa Lin, Guo-Zua Wu. 143-145 [doi]
• Implementation of intelligent home appliances based on IoTTsung-Han Tsai, Kung-Long Zhang. 146-148 [doi]
• A processor shield for software-based on-line self-testChing-Wen Lin, Chung-Ho Chen. 149-152 [doi]
• Edge-based moving object tracking algorithm for an embedded systemKai Xiang Yang, Ming-Hwa Sheu. 153-155 [doi]
• Effective model construction for enhanced prediction in example-based super-resolutionChun-Wei Chen, Fang-Kai Hsu, Der-Wei Yang, Jonas Wang, Ming-Der Shieh. 156-159 [doi]
• Low-cost prototype design of a portable ECG signal recorderShin-Chi Lai, Te-Hsuan Hung, Wen Chih Li, Yu-Syuan Jhang, Kuan-Ying Chang, Wen-Ho Juang, Ching-Hsing Luo. 160-163 [doi]
• Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data linksGain Kim, Yusuf Leblebici. 164-167 [doi]
• Fully coherent shaped offset QPSK demodulator architecture with superior hardware efficiencyDominik Rieth, Christoph Heller, Gerd Ascheid. 168-171 [doi]
• Narrowband interference suppression with symbol interleaving for UWB communication systemsEisaku Ogawa, Yosuke Sugiura, Tetsuya Shimamura. 172-175 [doi]
• The research of broadband MIMO millimeter wave transceiver system: Design and testFei Huang, Jianyi Zhou, Zhiqiang Yu, Binqi Yang, Ji Lan, Weichen Huang. 176-179 [doi]
• A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) methodGihoon Jung, Kyungrak Choi, Jongsun Park. 180-183 [doi]
• High-efficiency and cost-sharing architecture design of fast algorithm based multiple 4×4 and 8×8 forward transforms for multi-standard video encoderHao-Fan Hsu, Chia-Wei Chang, Chih-Peng Fan. 184-187 [doi]
• A design of a cost-effective look-up table for RGB-to-RGBW conversionSunwoong Kim, Hyuk-Jae Lee. 188-191 [doi]
• Efficient hole filling and depth enhancement based on texture image and depth map consistencyTing-An Chang, Jung-Ping Kuo, Jar-Ferr Yang. 192-195 [doi]
• Weighted peak ratio for estimating stereo confidence level using color similaritySanghun Kim, Chan Young Jang, Young-Hwan Kim. 196-197 [doi]
• Depth extraction using adaptive blur channel selection for dual aperture cameraKyungHo Kim, Yeongmin Lee, Hyun-Sang Park, Chong-Min Kyung. 198-201 [doi]
• Step shift: A fast image segmentation algorithm and its hardware implementation for next-generation sequencing fluorescence dataXiao-Xuan Huang, Chun-Hsien Ho, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu. 202-205 [doi]
• Implementation of a resource-constrained ECC processor with power analysis countermeasureZilong Liu, Dongsheng Liu, Xiangcheng Sun, Xuecheng Zou, Hui Lin. 206-209 [doi]
• Correlation-graph-based temperature sensor allocation for thermal-aware network-on-chip systemsKun-Chih Jimmy Chen, Yen-Po Lin, Kai-Yu Chiang, Yu-Hsien Chen. 210-213 [doi]
• Optimization of area and power in multi-mode power gating scheme for static memory elementsXing Su, Shinji Kimura. 214-217 [doi]
• FPGA-based real-time lane detection for advanced driver assistance systemsSeokha Hwang, Youngjoo Lee. 218-219 [doi]
• Implementation evaluation of scan-based attack against a Trivium cipher circuitDaisuke Oku, Masao Yanagisawa, Nozomu Togawa. 220-223 [doi]
• A simple method for finding all characteristic curves of piecewise-linear resistive circuits using an integer programming solverKiyotaka Yamamura, Ryota Watanabe. 224-227 [doi]
• Finding all solutions of piecewise-linear resistive circuits using excelKiyotaka Yamamura, Daiki Koyama. 228-231 [doi]
• A new decentralized discrete-time algorithm for estimating algebraic connectivity of multiagent networksKento Endo, Norikazu Takahashi. 232-235 [doi]
• Rigorous analysis of Arnold tongues in a manifold piecewise-linear circuitViet-Duc Le, Tadashi Tsubone, Naohiko Inaba. 236-239 [doi]
• Wide current range and high compliance-voltage bulk-driven current mirrors: Simple and cascodeKriangkrai Sooksood. 240-242 [doi]
• An ultra-low power and offset-insensitive CMOS subthreshold voltage referenceLidan Wang, Chenahang Zhan, Guofeng Li. 243-246 [doi]
• Methods for measuring loop-gain function of high-frequency DC-DC convertersXun Liu, Junmin Jiang, Philip K. T. Mok, Wing-Hung Ki. 247-249 [doi]
• An illumination aware single solar-cell VCO CCO based charge-pump energy harvesting system for SoC integrationR. P. Kartheek, Akash Gupta, Murali K. Rajendran, Ashudeb Dutta. 250-253 [doi]
• 0.6-V, Sub-nW, second-order lowpass filters using flipped voltage followersChutham Sawigun, Prajuab Pawarangkoon. 254-257 [doi]
• On-chip ESD protection design for radio-frequency power amplifier with large-swing-tolerance considerationGuan-Yi Li, Chun-Yu Lin. 258-261 [doi]
• Design of 5.5GHz LC oscillator using distributed grid of N-well in P-substrate inductorS. A. Enche Ab Rahim, Adel Barakat, Ramesh K. Pokharel. 262-264 [doi]
• Wide-band injection-locked frequency doublerWen Cheng Lai, Jheng-Wei Jhuang, Sheng-Lyang Jang, Guan-Yu Lin, Ching-Wen Hsue. 265-268 [doi]
• A tunable power amplifier employing digitally controlled accumulation-mode varactor array for 2.4-GHz short-range wireless communicationSanggil Kim, Donggu Im. 269-272 [doi]
• Interference measurement and analysis of full-duplex wireless system in 60 GHz bandHung-Wei Yang, Yongyu He, Chih-Wei Jen, Chun-Yi Liu, Shyh-Jye Jou, Xuefeng Yin, Meng Ma, Bingli Jiao. 273-276 [doi]
• Design and implementation of a low-latency, high-throughput sorted QR decomposition circuit for MIMO communicationsWei-Yang Chen, Daniel Günther, Chung-An Shen, Gerd Ascheid. 277-280 [doi]
• A generalized eigenvalue decomposition processor for multi-user MIMO precodingChun-An Chen, Yang Zao-Fu, Chiao-En Chen, Yuan-Hao Huang. 281-284 [doi]
• Design of a low-complexity O-QPSK transceiver with spatial modulation for internet-of-things applicationsChing-Hao Yang, Pei-Yun Tsai. 285-288 [doi]
• An IDD receiver of LDPC coded modulation scheme for flash memory applicationsMao-Ruei Li, Ting-Yu Kuan, Huang Chang Lee, Yeong-Luh Ueng. 289-292 [doi]
• Efficient hardware architecture of deterministic MPA decoder for SCMAChao Yang, Chuan Zhang, Shunqing Zhang, Xiaohu You. 293-296 [doi]
• A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessorsItaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura. 297-300 [doi]
• Power-flow simulation with visualization function based on IEEE common data formatShohei Sugino, Kazuhiro Okabe, Nobuyoshi Komuro, Hiroo Sekiya. 301-304 [doi]
• New class-E rectifier with low voltage stressXiuqin Wei, Hiroo Sekiya, Tadashi Suetsugu. 305-308 [doi]
• Particle swarm optimization for matrix converter of switching pattern designTakuya Shindo, Kenya Jin'no. 309-312 [doi]
• Firefly algorithm existing leader firefliesMasaki Takeuchi, Haruna Matsushita, Yoko Uwate, Yoshifumi Nishio. 313-316 [doi]
• Equidistant mixer-based frequency generation for 60 GHz FBMC transmitter topologiesOner Hanay, Erkan Bayram, David Bierbuesse, Renato Negra. 317-320 [doi]
• Design of a 8-taps, 10Gbps transmitter for automotive micro-controllersAndrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri. 321-324 [doi]
• Digital clock data recovery circuit fot S/PDIFJonghoon Kang, Chanho Lee. 325-326 [doi]
• A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detectorKi-Hyun Pyun, Dae Hyun Kwon, Woo-Young Choi. 327-329 [doi]
• A multi-tap inductor based 2.0-4.1 GHz wideband LC-oscillatorZaira Zahir, Gaurab Banerjee. 330-333 [doi]
• A 5-b 1-GS/s binary-search ADC in 90nm CMOSYung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chih Yeh. 334-335 [doi]
• Dynamic mapping method for static and dynamic performance improvement on current-steering digital-to-analog converterWei Mao, Yongfu Li, Chun-Huat Heng, Yong Lian. 336-339 [doi]
• A front-end circuit with 16-channel 12-bit 100-kSps RC-hybrid SAR ADC for industrial monitoring applicationZhelu Li, Jianxiong Xi, Lenian He, Kexu Sun. 340-343 [doi]
• A low jitter burst-mode clock and data recovery circuit with two symmetric VCO'sBum-Hee Choi, Kyung-Sub Son, Jin-Ku Kang. 344-347 [doi]
• A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADCJunjie Kong, Stephan Henzler, Doris Schmitt-Landsiedel, Liter Siek. 348-351 [doi]
• A systematic methodology for design and analysis of approximate array multipliersTakahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi. 352-354 [doi]
• Energy-efficient hybrid adder design by using inexact lower bits adderSunghyun Kim, Youngmin Kim. 355-357 [doi]
• Cooperative virtual channel router for adaptive hardwired FPGA network-on-chipF. F. Zakaria, Naa Latif, Shaiful Jahari Hashim, P. Ehkan, F. Z. Rokhani. 358-361 [doi]
• Mixed error correction scheme and its design optimization for soft-error tolerant datapathsJunghoon Oh, Mineo Kaneko. 362-365 [doi]
• Yield and power improvement method by post-silicon delay tuning and technology mappingHayato Mashiko, Yukihide Kohira. 366-369 [doi]
• A new online test and debug methodology for automotive camera image processing systemHyunggoy Oh, Inhyuk Choi, Sungho Kang. 370-371 [doi]
• A modified predictor-corrector method for tracing solution curvesKiyotaka Yamamura, Kiyoshi Adachi. 372-375 [doi]
• Voltage controlled memristor threshold logic gatesAkshay Kumar Maan, Alex Pappachen James. 376-379 [doi]
• Phase-controlled system design via mixed H∞ synthesis and nonlinear methodN. S. Ahmad, S. J. Abu Bakar. 380-383 [doi]
• Switching synchronization states of a ring of coupled chaotic circuits with one-direction delay effectsSeiya Kita, Yoko Uwate, Yoshifumi Nishio. 384-387 [doi]
• Efficient hardware architecture of deterministic MPA decoder for SCMAChao Yang, Chuan Zhang, Shunqing Zhang, Xiaohu You. 392-395 [doi]
• ASIC design of a low-complexity K-best Viterbi decoder for IoT applicationsHiromasa Kato, Thi Hong Tran, Yasuhiko Nakashima. 396-399 [doi]
• Low latency check node unit architecture for nonbinary LDPC decodingHuyen Thi Pham, Hanho Lee. 400-401 [doi]
• Efficient SOR-based detection and architecture for large-scale MIMO uplinkAnlan Yu, Chuan Zhang, Shunqing Zhang, Xiaohu You. 402-405 [doi]
• A low-power single-ended 11-bit SA-ADC with 1 V supply voltage and 2 V input voltage range for CMOS image sensorsJunbo Shim, Min-Kyu Kim, Seong-Kwan Hong, Oh-Kyong Kwon. 410-413 [doi]
• A low-complexity fast-locking digital PLL with multi-output bang-bang phase detectorQiwei Huang, Chenchang Zhan, Jinwook Burm. 418-420 [doi]
• A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applicationsManuel Delgado-Restituto, Manuel Carrasco-Robles, Rafaella Fiorelli, Antonio Jose Ginés Arteaga, Angel Rodriguez-Vazquez. 421-424 [doi]
• An efficient, wide range time-to-digital converter using cascaded time-interpolation stages for electrical impedance spectroscopySeongheon Shin, Soon-Jae Kweon, Jeong-Ho Park, Yong-Chang Choi, Hyung-Joun Yoo. 425-428 [doi]
• Near-infrared-ray and side-view video based drowsy driver detection system: Whether or not wearing glassesWei-Cheng Li, Wei-Liang Ou, Chih-Peng Fan, Chien-Hsiu Huang, Yi-Shian Shie. 429-432 [doi]
• Hardware design of histograms of oriented gradients based on local binary pattern and binarizationShen-Fu Hsiao, Jun-Mao Chan, Ching-Hui Wang. 433-435 [doi]
• Fast-Gaussian SIFT and its hardware architecture for keypoint detectionLiu Ke, Jun Wang, Xijun Zhao, Fan Liang. 436-439 [doi]
• Depth refinement on sparse-depth images using visual perception cuesMuhammad Umar Karim Khan, Asim Khan, Chong-Min Kyung. 440-443 [doi]
• Distributed video transcoding on a heterogeneous computing platformZhi-Hao Chang, Bih Fei Jong, Wei Jing Wong, M. L. Dennis Wong. 444-447 [doi]
• OL-SVR based soft-sensor for real-time estimation of solar irradianceJieming Ma, Ziqiang Bi, Yu Shi, Ka Lok Man, Xinyu Pan, Jian Wang. 448-451 [doi]
• The PnP Web Tag: A plug-and-play programming model for connecting IoT devices to the web of thingsFan Yang, Danny Hughes 0001, Nelson Matthys, Ka Lok Man. 452-455 [doi]
• Rectanna design for energy harvestingJing Chen Wang, Mark Leach, Zhao Wang, Ka Lok Man, Eng Gee Lim. 456-457 [doi]
• An exploration of usable authentication mechanisms for virtual reality systemsZhen Yu, Hai-Ning Liang, Charles Fleming, Ka Lok Man. 458-460 [doi]
• Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architectureTsai-Kan Chien, Lih-Yih Chiou, Chieh-Wen Cheng, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, Chih-I Wu. 461-464 [doi]
• A post-processing algorithm for reducing strong error effects in NAND flash memorySung-Rae Kim, Kijun Lee, Gyuyeol Kong, Myung-Kyu Lee, Dongmin Shin, Geunyeong Yu, Beomkyu Shin, Pilsang Yoon, Hongrak Son, Jun Jin Kong. 465-468 [doi]
• Low leakage mask vertical control TCAM for network routerYu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, Yen-Jen Chang. 469-472 [doi]
• Read margin analysis in an ReRAM crossbar arrayJaeHyun Seo, Byungsub Kim. 473-475 [doi]
• Sliced polar codesEran Hof. 476-479 [doi]
• A BIRA using fault-free memory region for area reductionChang Hyun Oh, Sae-Eun Kim, Joon-Sung Yang. 480-482 [doi]
• Low-frequency noise reduction technique for accelerometer readout circuitPo-Chang Wu, Chih-Yuan Yeh, Hann-Huei Tsai, Ying-Zong Juang. 483-486 [doi]
• A high background light subtraction circuit for long range time-of-flight camerasChandani Anand, Kapil Jainwal, Mukul Sarkar. 487-490 [doi]
• Modelling and analysis of signal flow platform implementation into retinal cell pathwayJason K. Eshraghian, Seungbum Baek, Kyoung-Rok Cho, Nicolangelo Iannella, Jun-Ho Kim, Yong-Sook Goo, Herbert H. C. Iu, Tyrone Fernando, Kamran Eshraghian. 491-494 [doi]
• Interface IC for breath analyzer with four three-electrode metal-oxide gas sensors and a humidity sensorJeong-Ho Park, Han-Won Cho, Soon-Jae Kweon, Hyung-Joun Yoo. 495-498 [doi]
• Dark current analysis of P-type and N-type pixels under total ionizing dose radiation effectsRan Zheng, Jia Wang. 499-501 [doi]
• Simultaneous layer-aware and region-aware partitioning for 3D ICYung-Hao Lai, Yang-Lang Chang, Jyh Perng Fang, Jie Lee. 502-505 [doi]
• A unified GDB-based source-transaction level SW/HW co-debuggingTsun-Hsin Chang, Shao-Chieh Hou, Ing-Jer Huang. 506-509 [doi]
• Profiling-based task graph extraction on multiprocessor system-on-chipSodam Han, Yonghee Yun, Young-Hwan Kim. 510-513 [doi]
• Calculating the probability of timing violation of F/F-controlled paths with timing variationsHyun-jeong Kwon, Young-Hwan Kim. 514-517 [doi]
• Unified HW/SW framework for efficient system level simulationNana Sutisna, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi. 518-521 [doi]
• Test access mechaism for stack test time reduction of 3-dimensional integrated circuitInhyuk Choi, Hyunggoy Oh, Sungho Kang. 522-525 [doi]
• Design optimization considering guiding template feasibility and redundant via insertion for directed self-assemblyShao-Yun Fang, Yun-Xiang Hong. 526-529 [doi]
• Machine learning (ML)-based lithography optimizationsSeongbo Shim, Suhyeong Choi, Youngsoo Shin. 530-533 [doi]
• Multiple-patterning lithography-aware routing for standard cell layout synthesisKuen-Wey Lin, Yih-Lang Li, Rung-Bin Lin. 534-537 [doi]
• Manufacturability-aware mask assignment in multiple patterning lithographyYukihide Kohira, Atsushi Takahashi 0001, Tomomi Matsui, Chikaaki Kodama, Shigeki Nojima, Satoshi Tanaka. 538-541 [doi]
• VLSI layout hotspot detection based on discriminative feature extractionHang Zhang, Haoyu Yang, Bei Yu, Evangeline F. Y. Young. 542-545 [doi]
• Design of low-dropout regulator using a-InGaZnO thin-film transistorsYongchan Kim, Hojin Lee. 546-547 [doi]
• A low-area 10b column driver with resistor-resistor-string DAC for mobile active-matrix LCDsJong-Seok Kim, Jin-O. Yoon, Byong-Deok Choi. 548-550 [doi]
• On-glass operational amplifier using solution-processed a-IGZO TFTsDaejung Kim, Keun-Yeong Choi, Hojin Lee. 551-553 [doi]
• Low-power counter for column-parallel CMOS image sensorsJong-Seok Kim, Jin-O. Yoon, Byong-Deok Choi. 554-556 [doi]
• Fingerprint pixel sensor array on a displayIn Hye Kang, Jun Young Hwang, Byung Seong Bae. 557-558 [doi]
• Design of a standing wave oscillator based PLLWei Zhang, Youde Hu, Keji Cui, Lebo Wang, Li-Rong Zheng. 559-562 [doi]
• An accurate design approach for two-stage CMOS operational amplifiersYushun Guo. 563-566 [doi]
• Design of a hybrid ring oscillator at 1.5/3.0 GHz with low power supply sensitivityVivek Sharma, Kapil Jainwal, Abhishek Tripathi. 567-570 [doi]
• High frame rate VGA CMOS image sensor using two-step single slope ADCsHimchan Park, Junan Lee, Jinwoo Kim, Yongsik Shin, Jinwook Burm. 571-572 [doi]
• Limited search sphere decoder and adaptive detector for NOMA with SU-MIMOI-Min Kuo, Wen-Ching Hu, Tzi-Dar Chiueh. 573-576 [doi]
• LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing enginesXin-Yu Shih, Po-Chun Huang, Yu-Chun Chen. 577-580 [doi]
• Analog filters design in VLC analog front-end receiver for reducing indoor ambient light noiseTrio Adiono, Angga Pradana, Rachmad Vidya Wicaksana Putra, Syifaul Fuada. 581-584 [doi]
• Efficient successive cancellation decoder for polar codes based on frozen bitsZhe-Yan Piao, Yeon-Jin Kim, Jin-Gyun Chung. 585-587 [doi]
• Architecture of WLAN channel estimatorsMy-Kieu Nguyen-Thi, Ik Joon Chang, Jinsang Kim. 588-590 [doi]
• Closed-form design of FIR frequency selective filter using discrete sine transformChien-Cheng Tseng, Su-Ling Lee. 591-594 [doi]
• Discrete fractional Hénon map based on digital fractional order integratorChien-Cheng Tseng, Su-Ling Lee. 595-598 [doi]
• Normal-form state-space realization of single frequency IIR notch filters and its application to adaptive notch filtersYoichi Hinamoto, Shotaro Nishimura. 599-602 [doi]
• Low complexity and quasi-linear phase IIR filters design based on iterative convex optimizationJinghong Tan, Jiajia Chen. 603-606 [doi]
• Multiplierless two-stage comb structure with an improved magnitude characteristicGordana Jovanovic-Dolecek, Alfonso Fernández-Vazquez. 607-610 [doi]
• Pixel-based pipeline hardware architecture for high-performance Haar-like feature extractionYuki Fujita, Fengwei An, Aiwen Luo, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch. 611-612 [doi]
• A dualband impedance transformer realized by fractional-order inductor and capacitorPeng Chen, Kai Yang, Tianliang Zhang. 613-616 [doi]
• Nonlinear inerter in the light of Chua's table of higher-order electrical elementsDalibor Biolek, Zdenek Biolek, Viera Biolkova, Zdenek Kolka. 617-620 [doi]
• Charging the capacitor via a (Memory) resistorZdenek Biolek, Dalibor Biolek, Viera Biolkova. 621-624 [doi]
• On using the cyclically-coupled QC-LDPC codes in future SSDsQing Lu, Chiu-Wing Sham, Francis C. M. Lau. 625-628 [doi]
• Synchronization phenomena in star-coupled van der pol oscillators by adding different frequency oscillatorsMinh Hai Tran, Kosuke Oi, Yoko Uwate, Yoshifumi Nishio. 629-632 [doi]
• TCAM-PUF with improved reliability and uniqueness for security improvementT. Nagakarthik, Jeong O. Kim, Tae Yang Kim, Joon Ho Kong, Jun Rim Choi. 633-634 [doi]
• PIM architecture exploration for HMCSangwoo Han, Hyeokjun Seo, Byoungjin Kim, Eui-Young Chung. 635-636 [doi]
• Electrochromic display driving scheme for high dynamic range image captureSeok-Jeong Song, Dowon Kim, Jeongrim Seo, Ki-Hyuk Seol, Hyoungsik Nam. 637-639 [doi]
• Self-contained built-in-self-test/repair transceivers for interconnects in 3DICsMyat Thu Linn Aung, Tony T. Kim. 640-641 [doi]
• A low power and low noise CMOS chopper amplifier for use in capacitive type accelerometerChih-Yuan Yeh, Jung-Tang Huang, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang. 642-645 [doi]
• Low-power, lightweight and reliability-enhanced current starved inverter based RO PUFsChao Qun Liu, Yuan Cao, Chip-Hong Chang. 646-649 [doi]
• Interceptive side channel attack on AES-128 wireless communications for IoT applicationsAli Akbar Pammu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee. 650-653 [doi]
• An advanced 3D format generation architecture for video and depthPin-Chen Kuo, Kuan-Ting Lee, Ching-Lun Chou, Chun-Wei Chang, Bin-Da Liu, Jar-Ferr Yang. 654-657 [doi]
• DeAr: A framework for power-efficient and flexible embedded digital signal processor designChi-Ming Lee, Yong-Jyun Huang, Chih-Wei Liu, Yarsun Hsu. 658-661 [doi]
• Analysis of a reconfigurable TEG array for high efficiency thermoelectric energy harvestingQiping Wan, Ying Khai Teh, Philip K. T. Mok. 662-665 [doi]
• Comparison of two SiGe 2-stage E-band power amplifier architecturesTobias Tired, Henrik Sjöland, Göran Jönsson, Johan Wernehag. 666-669 [doi]
• Analysis of non-ideal effects and electrochemical impedance spectroscopy of arrayed flexible NiO-based pH sensorSiao-Jie Yan, Jung-Chuan Chou, Yi-Hung Liao, Chih-Hsien Lai, Jian-Syun Chen, Bo-Yang Zhuang, Hsiang-Yi Chen, Ting-Wei Tseng. 670-673 [doi]
• System-level failure simulation and memory allocation scheme in 3D memoryJung Jin Lee, Joon-Sung Yang. 674-675 [doi]
• Random testing of C compilers based on test program generation by equivalence transformationKazuhiro Nakamura, Nagisa Ishiura. 676-679 [doi]
• Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCsSarang Kazeminia, Arefeh Soltani. 680-683 [doi]
• FPGA implementation of hamming code for increasing the frame rate of CAN communicationRonnie O. Serfa Juan, Min Woo Jeong, Hyeong-Woo Cha, Hi-Seok Kim. 684-687 [doi]
• An ultra-low power CMOS subthreshold voltage reference without requiring resistors or BJTsYang Liu, Chenchang Zhan, Lidan Wang. 688-690 [doi]
• Wide rear vehicle recognition using a fisheye lens camera imageJin-Seong Jeong, Hyun-Tae Kim, Bruce C. Kim, Sang-Bock Cho. 691-693 [doi]
• A low power relaxation oscillator with process insensitive auto-calibration schemeXin Lu, Bo Wang, Zhihuang Wen, Xiaojin Zhao, Yuan Cao, Amine Bermak. 694-697 [doi]
• Closed-loop transfer functions and frequency-point spectrum simulation of CCM buck convertersWing-Hung Ki, Lin Cheng, Chenchang Zhan. 698-701 [doi]
• Texture-based fast CU size decision algorithm for HEVC intra codingJae Myung Ha, Jong-Hyun Bae, Myung Hoon Sunwoo. 702-705 [doi]
• DC-20 GHz differential transmit/receieve DP4T switching matrix for radar-based target detectionA. Azhari, T. Kikkawa. 706-709 [doi]
• Low-power dual-precision table-based function evaluation supporting dynamic precision changesShen-Fu Hsiao, Kuei-Chun Huang. 710-712 [doi]
• TSV-aware 3-D IC structural planning with irregular die-sizeArko Dutt, Pranab Roy, Hafizur Rahaman. 713-716 [doi]
• KKT-condition based study on DVFS for heterogeneous task setMineo Kaneko. 717-720 [doi]
• A -34dBm sensitivity battery-less wake-up receiver with digital decoderNagaveni Vamsi, Sesha Sairam Ragulagadda, Ashudeb Dutta, Shiv Govind Singh. 721-724 [doi]
• Contrast enhancement using multiple mapping functions for power reduction in OLED displayChan Young Jang, Sanghun Kim, Young-Hwan Kim. 725-726 [doi]
• Text information acquisition method of traffic signs for autonomous navigationHyun-Tae Kim, Jin-Seong Jeong, Bruce C. Kim, Sang-Bock Cho. 727-729 [doi]
• A 0.9V, 3.1-10.6 GHz CMOS LNA with high gain and wideband input match in 90 nm CMOS processSunil Kumar Pandey, P. N. Kondekar, Kaushal Nigam, Dheeraj Sharma. 730-733 [doi]
• 2 per Channel in 65-nm CMOSSeyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim. 734-735 [doi]
• Live demonstration: MINDS - Meshed and internet networked devices system for smart home: Track selection: Embedded systemsTrio Adiono, Maulana Yusuf Fathany, Rachmad Vidya Wicaksana Putra, Khilda Afifah, Muhammad Husni Santriaji, Braham Lawas Lawu, Syifaul Fuada. 736-737 [doi]
• Live demonstration: MorFPGA duo platform with dual-camera supportChun-Ming Huang, Chih-Chyau Yang, Chien-Ming Wu, Chun-Wen Cheng, Chun-Yu Chen, Yi-Jun Liu. 738-739 [doi]
• Live demonstration: Signal flow platform implementation into retinal cell pathwaySeungbum Baek, Jason K. Eshraghian, Kyoung-Rok Cho, Nicolangelo Iannella, Jun-Ho Kim, Herbert H. C. Iu, Tyrone Fernando, Kamran Eshraghian. 740-741 [doi]
• Live demonstration: Memristor synaptic array with FPGA-implemented neurons for neuromorphic pattern recognitionSon Ngoc Truong, Khoa Van Pham, Wonsun Yang, Kyeong-Sik Min, Yawar Abbas, Chi Jung Kang. 742-743 [doi]
• Live demonstration: An FPGA based hardware compression accelerator for Hadoop systemSang Muk Lee, Jung-Hwan Oh, Ji-Hoon Jang, Seong Mo Lee, Ji Kwang Kim, Seung Eun Lee. 744-745 [doi]
• Live demonstration: AHB based digital filter for low power mobile healthcare systemOh Seong Gwon, Ji Kwang Kim, Jung Woo Shin, Seung Eun Lee. 746-747 [doi]
• Live demonstration: CAN FD controller for in-vehicle networkJung Woo Shin, Jung-Hwan Oh, Sang Muk Lee, Seung Eun Lee. 748-749 [doi]