Chih-Chang Lin - researchr alias

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Viewing Publication 1 - 16 from 16

2020

Design Guidelines of Social-Assisted Robots for the Elderly: A Mixed Method Systematic Literature ReviewChih-Chang Lin, Hao-Yu Liao, Fang-Wu Tung. hci 2020: 90-104 [doi]

2019

2014

8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOSTsung-Ching Huang, Tao-Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Fu-Lung Hsueh. isscc 2014: 144-145 [doi]

1999

Logic synthesis for engineering changeChih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska. tcad, 18(3):282-292, 1999. [doi]

1998

Cost-free scan: a low-overhead scan path designChih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen. tcad, 17(9):852-861, 1998. [doi]

Test-point insertion: scan paths through functional logicChih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee. tcad, 17(9):838-851, 1998. [doi]

A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAsPeichen Pan, Chih-Chang Lin. fpga 1998: 35-42 [doi]

1997

On designing universal logic blocks and their application to FPGA designChih-Chang Lin, Malgorzata Marek-Sadowska. tcad, 16(5):519-527, 1997. [doi]

1996

Sequential Permissible Functions and their Application to Circuit OptimizationChih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee. date 1996: 334-339 [doi]

Test Point Insertion: Scan Paths through Combinational LogicChih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee. dac 1996: 268-273 [doi]

1995

1994

Universal logic gate for FPGA designChih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin. iccad 1994: 164-168 [doi]

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