Table of Contents

• A Novel Predictable Segmented FPGA Routing ArchitectureEmil S. Ochotta, Patrick J. Crotty, Charles R. Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard C. Li, Joseph D. Linoff, Luan Ngo, Hy V. Nguyen, Kerry M. Pierce, Douglas P. Wieland, Jennifer Zhuang, Scott S. Nance. 3-11 [doi]
• More Wires and Fewer LUTs: A Design Methodology for FPGAsAtsushi Takahara, Toshiaki Miyazaki, Takahiro Murooka, Masaru Katayama, Kazuhiro Hayashi, Akihiro Tsutsui, Takaki Ichimori, Ken-nosuke Fukami. 12-19 [doi]
• Optimizations for a Highly Cost-Efficient Programmable Logic ArchitectureKerry Veenstra, Bruce Pedersen, Jay Schleicher, Chiakang Sung. 20-24 [doi]
• Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture EvaluationJason Cong, Yean-Yow Hwang. 27-34 [doi]
• A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAsPeichen Pan, Chih-Chang Lin. 35-42 [doi]
• A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA SystemsMohammed A. S. Khalid, Jonathan Rose. 45-54 [doi]
• Managing Pipeline-Reconfigurable FPGAsSrihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas. 55-64 [doi]
• Configuration Prefetch for Single Context Reconfigurable CoprocessorsScott Hauck. 65-74 [doi]
• Circuit Partitioning with Complex Resource Constraints in FPGAsHuiqun Liu, Kai Zhu, D. F. Wong. 77-84 [doi]
• Timing Driven Floorplanning on Programmable Hierarchical TargetsS. A. Senouci, A. Amoura, Helena Krupnova, Gabriele Saucier. 85-92 [doi]
• Bridging Fault Detection in FPGA Interconnects Using ::::I::DDQ::::::Lan Zhao, D. M. H. Walker, Fabrizio Lombardi. 95-104 [doi]
• Efficiently Supporting Fault-Tolerance in FPGAsJohn Lach, William H. Mangione-Smith, Miodrag Potkonjak. 105-115 [doi]
• Constraints from Hell: How to Tell Makes a Good FPGA (Panel)Jonathan Rose, Sinan Kaptanoglu, Clive McCarthy, Rob Smith, Sandip Vij, Steve Taylor. 117-119 [doi]
• Fast Module Mapping and Placement for Datapaths in FPGAsTimothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek. 123-132 [doi]
• Fast Integrated Tools for Circuit Design with FPGAsStephan W. Gehring, Stefan H.-M. Ludwig. 133-139 [doi]
• A Fast Routability-Driven Router for FPGAsJordan S. Swartz, Vaughn Betz, Jonathan Rose. 140-149 [doi]
• Scheduling Designs into a Time-Multiplexed FPGASteven Trimberger. 153-160 [doi]
• Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAsDouglas Chang, Malgorzata Marek-Sadowska. 161-167 [doi]
• SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory ArraysSteven J. E. Wilton. 171-178 [doi]
• Technology Mapping for FPGAs with Embedded Memory BlocksJason Cong, Songjie Xu. 179-188 [doi]
• A Survey of CORDIC Algorithms for FPGA Based ComputersRay Andraka. 191-200 [doi]
• FPGA-Based Sonar ProcessingPaul Graham, Brent E. Nelson. 201-208 [doi]
• Evolving Computer Programs Using Rapidly Reconfigurable Field-Programmable Gate Arrays and Genetic ProgrammingJohn R. Koza, Forrest H. Bennett III, Jeffrey L. Hutchings, Stephen L. Bade, Martin A. Keane, David Andre. 209-219 [doi]
• High-Performance Carry Chains for FPGAsScott Hauck, Matthew M. Hosler, Thomas W. Fry. 223-233 [doi]
• A Coarse-Grained FPGA Architecture for High-Performance FIR FilteringJames R. Anderson, Siddharth Sheth, Kaushik Roy. 234-244 [doi]
• An LPGA with Foldable PLA-style Logic BlocksJason Helge Anderson, Stephen Dean Brown. 244-252 [doi]
• Advantages of the XC6000 Architecture for Embedded System Design (Abstract)Karlheinz Weiß, Ronny Kistner, Arno Kunzmann, Wolfgang Rosenstiel. 255 [doi]
• A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract)Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda. 255 [doi]
• Design of a Three-Dimensional FPGA for Reconfigurable Computing Machines (Abstract)Silviu M. S. A. Chiricescu, Mankuan Michael Vai. 256 [doi]
• Block and IP Wrapping for Efficient Design on FPGAs (Abstract)Helena Krupnova, B. Behnam, Gabriele Saucier. 256 [doi]
• A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract)David Jefferson, Srinivas Reddy, Christopher Lane, Ninh Ngo, Wanli Chang, Manuel Mijia, Ketan Zaveri, Cameron McClintock, Richard Cliff. 256 [doi]
• FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract)Hanho Lee, Sarvesh Shrivastava, Gerald E. Sobelman. 257 [doi]
• GART: A New, Flexible Placement and Routing Tool for Research on FPGA Architectures (Abstract)Jo Depreitere, Herwig Van Marck, Jan Van Campenhout. 257 [doi]
• FPGA Circuit Optimization Based on Block Integration (Abstract)Takenori Kouda, Yahiko Kambayashi. 257 [doi]
• Implementation of IEEE Single-Precision Floating-Point Operations on FPGAs (Abstract)Walter B. Ligon III, Greg Monn, S. P. McMillan, Kevin Schoonover, Fred Stivers, Keith D. Underwood. 258 [doi]
• Hardware Implementation of Generalized Profile Search on the GENSTROM Machine (Abstract)Emeka Mosanya, Jean-Michel Puiatti, Eduardo Sanchez. 258 [doi]
• High-Level Synthesis Using Genetic Algorithms for Dynamically Reconfigurable FPGAs (Abstract)Xue-Jie Zhang, Kam-Wing Ng, Gilbert H. Young. 258 [doi]
• Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract)Franco Fummi, A. Marshall, Laura Pozzi, Mariagiovanna Sami. 258 [doi]
• Partial FPGA Rearrangement by Local Repacking (Abstract)Oliver Diessel, Hossam A. ElGindy. 259 [doi]
• Mapping Multiplication Algorithms into a Family of LUT-based FPGAs (Abstract)Manuel Jiménez, Chin-Long Wey, Michael A. Shanblatt. 259 [doi]
• Rapid Prototyping of Multi-Recommendation Modem (Abstract)Abdellatif Mtibaa, Mohamed Abid, Rached Tourki. 260 [doi]
• Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract)Wai-Kei Mak, D. F. Wong. 260 [doi]
• Reconfigurable Processing for Robust Navigation and Control (Abstract)Jeanette F. Arrigo, Kevin J. Page, Paul M. Chau, N. C. Tien. 260 [doi]
• REMARC: Reconfigurable Multimedia Array Coprocessor (Abstract)Takashi Miyamori, Kunle Olukotun. 261 [doi]
• Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract)Hidehisa Nagano, Takayuki Suyama, Akira Nagoya. 261 [doi]
• RENCO: A Reconfigurable Network Computer (Abstract)Jacques-Olivier Haenni, Erik Bruchez, Emeka Mosanya, Eduardo Sanchez. 261 [doi]
• FPGA Implementation of an ATM Traffic Shaper: ATS (Abstract)Jesus Crespo, Juan Carlos Diaz, Pimitivo Matas. 262 [doi]