Yean-Yow Hwang - researchr alias

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Viewing Publication 1 - 9 from 9

2006

Protecting Combinational Logic Synthesis SolutionsDarko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong. tcad, 25(12):2687-2696, 2006. [doi]

2001

Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mappingJason Cong, Yean-Yow Hwang. tcad, 20(9):1077-1090, 2001. [doi]

2000

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designsJason Cong, Yean-Yow Hwang. todaes, 5(2):193-225, 2000. [doi]

1999

Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast InterconnectionsJason Cong, Yean-Yow Hwang, Songjie Xu. dac 1999: 373-378 [doi]

1998

Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture EvaluationJason Cong, Yean-Yow Hwang. fpga 1998: 27-34 [doi]

Intellectual property protection by watermarking combinational logic synthesis solutionsDarko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong. iccad 1998: 194-198 [doi]

1997

Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and MappingJason Cong, Yean-Yow Hwang. fpga 1997: 35-42 [doi]

1996

Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA DesignJason Cong, Yean-Yow Hwang. dac 1996: 726-729 [doi]

1995

Simultaneous Depth and Area Minimization in LUT-based FPGA MappingJason Cong, Yean-Yow Hwang. fpga 1995: 68-74 [doi]

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