Abstract is missing.
- On Designing ULM-based FPGA Logic ModulesShashidhar Thakur, D. F. Wong. 3-9 [doi]
- Using Architectural Families to Increase FPGA Speed and DensityVaughn Betz, Jonathan Rose. 10-16 [doi]
- Design of FPGAs with Area I/O for Field Programmable MCMVijayshri Maheshwari, Joel Darnauer, John Ramirez, Wayne Wei-Ming Dai. 17-23 [doi]
- TIERS: Topology Independent Pipelined Routing and Scheduling for VirtualWire CompilationCharles Selvidge, Anant Agarwal, Matthew Dahl, Jonathan Babb. 25-31 [doi]
- Logic Partition Orderings for Multi-FPGA SystemsScott Hauck, Gaetano Borriello. 32-38 [doi]
- Hardware Assists for High Performance Computing Using a Mathematics of ArraysH. Pottinger, W. Eatherton, J. Kelly, T. Schiefelbein, L. R. Mullin, R. Ziegler. 39-45 [doi]
- High-Energy Physics on DECPeRLe-1 Programmable Active MemoryLaurent Moll, Jean Vuillemin, Philippe Boucard. 47-52 [doi]
- HGA: A Hardware-Based Genetic AlgorithmStephen D. Scott, Ashok Samal, Sharad C. Seth. 53-59 [doi]
- The Design of RPM: An FPGA-based Multiprocessor EmulatorKoray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois. 60-66 [doi]
- Simultaneous Depth and Area Minimization in LUT-based FPGA MappingJason Cong, Yean-Yow Hwang. 68-74 [doi]
- Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and BussesBaher Haroun, Behzad Sajjadi. 75-81 [doi]
- On Nominal Delay Minimization in LUT-based FPGA Technology MappingJason Cong, Yuzheng Ding. 82-88 [doi]
- Revisiting the Cascade Circuit in Logic Cells of Lookup Table Based FPGAsNam Sung Woo. 90-96 [doi]
- Architecture of Centralized Field-Configurable MemorySteven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic. 97-103 [doi]
- A Field-Programmable Mixed-Analog-Digital ArrayP. Glenn Gulak, Paul Chow. 104-109 [doi]
- PathFinder: A Negotiation-based Performance-driven Router for FPGAsLarry McMurchie, Carl Ebeling. 111-117 [doi]
- Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAsAnmol Mathur, K.-C. Chen, C. L. Liu. 118-124 [doi]
- Testing of Uncustomized Segmented Channel Field Programmable Gate ArraysTong Liu, Wei-Kang Huang, Fabrizio Lombardi. 125-131 [doi]
- Spectral-Based Multi-Way FPGA PartitioningPak K. Chan, Martine D. F. Schlag, Jason Y. Zien. 133-139 [doi]
- Multi-way System Partitioning into a Single Type or Multiple Types of FPGAsDennis J.-H. Huang, Andrew B. Kahng. 140-145 [doi]
- Multiple FPGA Partitioning with Performance OptimizationKalapi Roy-Neogi, Carl Sechen. 146-152 [doi]
- Techniques for FPGA Implementation of Video Compression SystemsBrian Schoner, John D. Villasenor, Steve Molloy, Rajeev Jain. 154-159 [doi]
- An SBus Monitor BoardH. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask. 160-166 [doi]
- High-Level Bit-Serial Datapath Synthesis for Multi-FPGA SystemsTsuyoshi Isshiki, Wayne Wei-Ming Dai. 167-173 [doi]