Klaus Eckl - researchr alias

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Viewing Publication 1 - 9 from 9

2003

Technologienahe Retimingverfahren zur Optimierung synchroner digitaler SchaltungenKlaus Eckl. PhD thesis, Technical University Munich, 2003.

Performance-Directed Retiming for FPGAs Using Post-Placement Delay InformationUlrich Seidl, Klaus Eckl, Frank M. Johannes. date 2003: 10770-10777 [doi]

1999

Retiming Sequential Circuits with Multiple Register ClassesKlaus Eckl, Christian Legl. date 1999: 650 [doi]

A Practical Approach to Multiple-Class RetimingKlaus Eckl, Jean Christophe Madre, Peter Zepter, Christian Legl. dac 1999: 237-242 [doi]

Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAsBernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich. todaes, 4(3):313-350, 1999. [doi]

1998

Computing support-minimal subfunctions during functional decompositionChristian Legl, Bernd Wurth, Klaus Eckl. tvlsi, 6(3):354-363, 1998. [doi]

1996

Performance-Directed Technology-Mapping for LUT-Based FPGAs - What Role Do Decomposition and Covering Play?Christian Legl, Klaus Eckl, Bernd Wurth. fpl 1996: 14-23

An Implicit Algorithm for Support Minimization during Functional DecompositionChristian Legl, Bernd Wurth, Klaus Eckl. date 1996: 412-419 [doi]

1995

Functional Multiple-Output Decomposition: Theory and an Implicit AlgorithmBernd Wurth, Klaus Eckl, Kurt Antreich. dac 1995: 54-59 [doi]

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