Table of Contents

• IC Design Challenges for Ambient IntelligenceEmile H. L. Aarts, Raf Roovers. 10002-10007 [doi]
• Semiconductor ChallengesAndrea Cuomo. 10008-10009 [doi]
• Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World ConceptsMenno Lindwer, Diana Marculescu, Twan Basten, Rainer Zimmermann, Radu Marculescu, Stefan Jung, Eugenio Cantatore. 10010-10017 [doi]
• Improving the Efficiency of Memory Partitioning by Address ClusteringAlberto Macii, Enrico Macii, Massimo Poncino. 10018-10023 [doi]
• A New Algorithm for Energy-Driven Data Compression in VLIW Embedded ProcessorsAlberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon. 10024-10029 [doi]
• Power Efficiency through Application-Specific Instruction Memory TransformationsPeter Petrov, Alex Orailoglu. 10030-10035 [doi]
• Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable ArchitecturesMarcos Sanchez-Elez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida. 10036-10043 [doi]
• Circuit and Platform Design Challenges in Technologies beyond 90nmBill Grundmann, Rajesh Galivanche, Sandip Kundu. 10044-10049 [doi]
• Global Wire Bus Configuration with Minimum Delay UncertaintyLi-Da Huang, Hung-Ming Chen, D. F. Wong. 10050-10055 [doi]
• Timing Verification with Crosstalk for Transparently Latched CircuitsHai Zhou. 10056-10061 [doi]
• Statistical Timing Analysis Using BoundsAseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula. 10062-10067 [doi]
• Reduced Delay Uncertainty in High Performance Clock Distribution NetworksDimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman. 10068-10075 [doi]
• Scaling into Ambient IntelligenceTwan Basten, Luca Benini, Anantha Chandrakasan, Menno Lindwer, Jie Liu, Rex Min, Feng Zhao. 10076-10083 [doi]
• Masking the Energy Behavior of DES EncryptionHendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang 0002. 10084-10089 [doi]
• Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded SystemsDong Wu, Bashir M. Al-Hashimi, Petru Eles. 10090-10095 [doi]
• Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power ApplicationsLih-Yih Chiou, Swarup Bhunia, Kaushik Roy. 10096-10103 [doi]
• Virtual Compression through Test Vector Stitching for Scan Based DesignsWenjing Rao, Alex Orailoglu. 10104-10109 [doi]
• Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback ArchitectureNahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch. 10110-10115 [doi]
• A Technique for High Ratio LZW CompressionMichael J. Knieser, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, David R. McIntyre. 10116-10121 [doi]
• Fast Computation of Data Correlation Using BDDsZhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski. 10122-10129 [doi]
• RTOS Modeling for System Level DesignAndreas Gerstlauer, Haobo Yu, Daniel Gajski. 10130-10135 [doi]
• Modeling and Integration of Peripheral Devices in Embedded SystemsShaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi. 10136-10141 [doi]
• Systemic Embedded Software Generation from SystemCFernando Herrera, Hector Posadas, Pablo Sánchez, Eugenio Villar. 10142-10149 [doi]
• Noise Macromodel for Radio Frequency Integrated CircuitsYang Xu, Xin Li, Peng Li, Lawrence T. Pileggi. 10150-10155 [doi]
• Approximation Approach for Timing Jitter Characterization in Circuit SimulatorsMark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney. 10156-10161 [doi]
• A Model of Computation for Continuous-Time ?-? ModulatorsEwout Martens, Georges G. E. Gielen. 10162-10167 [doi]
• Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description LanguagesR. Castro-López, Francisco V. Fernández, F. Medeiro, Ángel Rodríguez-Vázquez. 10168-10175 [doi]
• Securing Mobile Appliances: New Challenges for the System DesignerAnand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater. 10176-10183 [doi]
• Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded SystemsPaul Pop, Petru Eles, Zebo Peng. 10184-10189 [doi]
• A General Framework for Analysing System Properties in Platform-Based Embedded System DesignsSamarjit Chakraborty, Simon Künzli, Lothar Thiele. 10190-10195 [doi]
• Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space ExplorationGeorge Logothetis, Klaus Schneider. 10196-10203 [doi]
• Rapid Prototyping of Flexible Embedded Systems on Multi-DSP ArchitecturesBernhard Rinner, Martin Schmid, Reinhold Weiss. 10204-10211 [doi]
• DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed TestersMuhammad Nummer, Manoj Sachdev. 10212-10217 [doi]
• Extending JTAG for Testing Signal Integrity in SoCsNisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani. 10218-10223 [doi]
• EBIST: A Novel Test Generator with Built-In Fault Detection CapabilityDhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty. 10224-10229 [doi]
• A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault DiagnosisChunsheng Liu, Krishnendu Chakrabarty. 10230-10237 [doi]
• Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency DetectorsPiet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen. 10238-10243 [doi]
• A New Simulation Technique for Periodic Small-Signal AnalysisMark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney. 10244-10249 [doi]
• Generalized Posynomial Performance ModelingTom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen. 10250-10255 [doi]
• HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated CircuitsBart De Smedt, Georges G. E. Gielen. 10256-10263 [doi]
• High-Level Allocation to Minimize Internal Hardware WastageMaría C. Molina, José M. Mendías, Román Hermida. 10264-10269 [doi]
• Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive DesignsSumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau. 10270-10275 [doi]
• Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic UnitsEuiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya. 10276-10281 [doi]
• Automated Bus Generation for Multiprocessor SoC DesignKyeong Keol Ryu, Vincent John Mooney. 10282-10289 [doi]
• Online Scheduling for Block-Partitioned Reconfigurable Devices Herbert Walder, Marco Platzner. 10290-10295 [doi]
• Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo SchedulingBingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins. 10296-10301 [doi]
• Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded SystemsSebastian Lange, Udo Kebschull. 10302-10309 [doi]
• A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation AlgorithmsSatoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara. 10310-10315 [doi]
• A Novel, Low-Cost Algorithm for Sequentially Untestable Fault IdentificationManan Syal, Michael S. Hsiao. 10316-10321 [doi]
• Non-Enumerative Path Delay Fault Diagnosis Saravanan Padmanaban, Spyros Tragoudas. 10322-10327 [doi]
• Delay Defect Diagnosis Based Upon Statistical Timing Models - The First StepAngela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir. 10328-10335 [doi]
• Introduction to Hardware Abstraction Layers for SoCSungjoo Yoo, Ahmed Amine Jerraya. 10336-10337 [doi]
• Hardware/Software Partitioning of Operating SystemsVincent John Mooney. 10338-10339 [doi]
• Embedded Software in Digital AM-FM ChipsetM. Sarlotte, B. Candaele, J. Quevremont, D. Merel. 10340-10343 [doi]
• Packetized On-Chip Interconnect Communication Analysis for MPSoCTerry Tao Ye, Luca Benini, Giovanni De Micheli. 10344-10349 [doi]
• Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on ChipEdwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, E. Waterlander. 10350-10355 [doi]
• Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors Frank Gilbert, Michael J. Thul, Norbert Wehn. 10356-10363 [doi]
• Development and Application of Design Transformations in ForSyDeIngo Sander, Axel Jantsch, Zhonghai Lu. 10364-10369 [doi]
• System Level Specification in LavaSatnam Singh. 10370-10375 [doi]
• Formal Semantics of Synchronous SystemCAshraf Salem. 10376-10381 [doi]
• Introspection in System-Level Language Frameworks: Meta-Level vs. IntegratedFrederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta. 10382-10387 [doi]
• SystemC-AMS Requirements, Design Objectives and RationaleAlain Vachoux, Christoph Grimm, Karsten Einwich. 10388-10395 [doi]
• Parallel Processing Architectures for Reconfigurable SystemsKees A. Vissers. 10396-10397 [doi]
• Different Approaches to Add Reconfigurability in a SoC ArchitectureBhusan Gupta, Michele Borgatti. 10398-10398 [doi]
• A Lightweight Approach for Embedded Reconfiguration of FPGAsBrandon Blodget, Scott McMillan, Patrick Lysaght. 10399-10401 [doi]
• Creating Value Through TestErik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller. 10402-10409 [doi]
• Control Flow Driven Splitting of Loop Nests at the Source Code Level Heiko Falk, Peter Marwedel. 10410-10415 [doi]
• Data Space Oriented Scheduling in Embedded SystemsMahmut T. Kandemir, Guangyu Chen, Wei Zhang 0002, Ibrahim Kolcu. 10416-10421 [doi]
• Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo SchedulingSatish Pillai, Margarida F. Jacome. 10422-10427 [doi]
• An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static SchedulingAntonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev. 10428-10435 [doi]
• Time Budgeting in a Wireplanning ContextJurjen Westra, Dirk-Jan Jongeneel, Ralph H. J. M. Otten, Chandu Visweswariah. 10436-10441 [doi]
• Interconnect Planning with Local Area Constrained RetimingRuibing Lu, Cheng-Kok Koh. 10442-10447 [doi]
• A Novel Metric for Interconnect Architecture PerformanceParthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu. 10448-10455 [doi]
• Specification of Non-Functional Intellectual Property ComponentsJianwen Zhu, Wai Sum Mong. 10456-10461 [doi]
• Profile-Driven Selective Code CompressionYuan Xie, Wayne Wolf, Haris Lekatsas. 10462-10467 [doi]
• Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band ReceiverChengzhi Pan, Nader Bagherzadeh, Amir Hosein Kamalizad, Arezou Koohi. 10468-10475 [doi]
• Panel Title: Reconfigurable Computing - Different PerspectivesWolfgang Rosenstiel, Rudy Lauwereins, Ivo Bolsens, Chris Rowen, Yankin Tanurhan, Kees A. Vissers, S. Wang. 10476-10477 [doi]
• RF-BIST: Loopback Spectral Signature AnalysisDoris Lupea, Udo Pursche, Hans-Joachim Jentschel. 10478-10483 [doi]
• Optimizing Stresses for Testing DRAM Cell Defects Using Electrical SimulationZaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter. 10484-10489 [doi]
• On Modeling Cross-Talk FaultsSujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti. 10490-10495 [doi]
• Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked LoopsMartin John Burbidge, Jim Tijou, Andrew Richardson. 10496-10503 [doi]
• Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software ApplicationsVenkata Syam P. Rapaka, Diana Marculescu. 10504-10509 [doi]
• Runtime Code Parallelization for On-Chip MultiprocessorsMahmut T. Kandemir, Wei Zhang 0002, Mustafa Karaköy. 10510-10515 [doi]
• SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor PlatformsPaul Marchal, José Ignacio Gómez, Luis Piñuel, Davide Bruni, Luca Benini, Francky Catthoor, Henk Corporaal. 10516-10523 [doi]
• Modeling and Evaluation of Substrate Noise Induced by InterconnectsFerran Martorell, Diego Mateo, Xavier Aragonès. 10524-10529 [doi]
• Model-Order Reduction Based on PRONY s MethodMakram M. Mansour, Amit Mehrotra. 10530-10535 [doi]
• Combined FDTD/Macromodel Simulation of Interconnected Digital DevicesStefano Grivet-Talocia, Igor S. Stievano, Ivan A. Maio, Flavio G. Canavero. 10536-10541 [doi]
• Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address BusesTiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf. 10542-10549 [doi]
• Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction LayerSungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya. 10550-10555 [doi]
• Flexible and Formal Modeling of Microprocessors with Application to Retargetable SimulationWei Qin, Sharad Malik. 10556-10561 [doi]
• Instruction Set Emulation for Rapid Prototyping of SoCs Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel. 10562-10569 [doi]
• Hardware/Software Design Space Exploration for a Reconfigurable ProcessorAlberto La Rosa, Luciano Lavagno, Claudio Passerone. 10570-10575 [doi]
• From C Programs to the Configure-Execute ModelJoão M. P. Cardoso, Markus Weinhardt. 10576-10581 [doi]
• FPGA-Based Implementation of a Serial RSA ProcessorAntonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Nicola Mazzocca. 10582-10589 [doi]
• Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-RepairMichael Nicolaidis, Nadir Achouri, Slimane Boutobza. 10590-10595 [doi]
• Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability MetricPetros Oikonomakos, Mark Zwolinski, Bashir M. Al-Hashimi. 10596-10601 [doi]
• An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined MicroprocessorMaurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 10602-10607 [doi]
• High Speed and Highly Testable Parallel Two-Rail Code CheckerMartin Omaña, Daniele Rossi, Cecilia Metra. 10608-10615 [doi]
• Safe Automotive Software DevelopmentKen Tindell, Hermann Kopetz, Fabian Wolf, Rolf Ernst. 10616-10623 [doi]
• Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying CircuitsPetr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay. 10624-10629 [doi]
• Linear Model-Based Error Identification and Calibration for Data ConvertersCarsten Wegener, Michael Peter Kennedy. 10630-10635 [doi]
• Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A ConvertersMiquel Albiol, José Luis González, Eduard Alarcón. 10636-10641 [doi]
• Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN ReceiverWolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. 10642-10649 [doi]
• Analytical Design Space Exploration of Caches for Embedded SystemsArijit Ghosh, Tony Givargis. 10650-10655 [doi]
• Fast and Accurate Multiprocessor Architecture Exploration with Symbolic ProgramsVladimir D. Zivkovic, Erwin A. de Kock, Pieter van der Wolf, Ed F. Deprettere. 10656-10661 [doi]
• Design Space Exploration for a Wireless Protocol on a Reconfigurable PlatformLaura Vanzago, Bishnupriya Bhattacharya, Joel Cambonie, Luciano Lavagno. 10662-10667 [doi]
• A First Step Towards Hw/Sw Partitioning of UML SpecificationsWilliam Fornaciari, P. Micheli, Fabio Salice, L. Zampella. 10668-10673 [doi]
• Multi-Granularity Metrics for the Era of Strongly Personalized SOCsYannick Le Moullec, Nahla Ben Amor, Jean-Philippe Diguet, Mohamed Abid, Jean Luc Philippe. 10674-10681 [doi]
• Energy Estimation for Extensible ProcessorsYunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 10682-10687 [doi]
• Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC ArchitecturesJingcao Hu, Radu Marculescu. 10688-10693 [doi]
• Chromatic Encoding: A Low Power Encoding Technique for Digital Visual InterfaceWei-Chung Cheng, Massoud Pedram. 10694-10699 [doi]
• MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital FiltersHunsoo Choo, Khurram Muhammad, Kaushik Roy. 10700-10705 [doi]
• Transport Protocol Optimization for Energy Efficient Wireless Embedded SystemsDavide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi. 10706-10713 [doi]
• Low-Cost Software-Based Self-Testing of RISC Processor CoresNektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian. 10714-10719 [doi]
• A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash MemoriesPaolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 10720-10725 [doi]
• Test Data Compression: The System Integrator s PerspectivePaul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici. 10726-10731 [doi]
• Time Domain Multiplexed TAM: Implementation and ComparisonZahra Sadat Ebadi, André Ivanov. 10732-10737 [doi]
• Layout-Driven SOC Test Architecture Design for Test Time and Wire Length MinimizationSandeep Kumar Goel, Erik Jan Marinissen. 10738-10741 [doi]
• Delay Fault Testing of Core-Based Systems-on-a-ChiQiang Xu, Nicola Nicolici. 10744-10752 [doi]
• Reducing Multi-Valued Algebraic Operations to BinaryJie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton. 10752-10757 [doi]
• Combination of Lower Bounds in Exact BDD MinimizationRüdiger Ebendt, Wolfgang Günther, Rolf Drechsler. 10758-10763 [doi]
• Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power EstimationAna T. Freitas, Arlindo L. Oliveira. 10764-10769 [doi]
• Performance-Directed Retiming for FPGAs Using Post-Placement Delay InformationUlrich Seidl, Klaus Eckl, Frank M. Johannes. 10770-10777 [doi]
• Exploring High Bandwidth Pipelined Cache Architecture for Scaled TechnologyAmit Agarwal, Kaushik Roy, T. N. Vijaykumar. 10778-10783 [doi]
• Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow AggregationG. Surendra, Subhasis Banerjee, S. K. Nandy. 10784-10789 [doi]
• On-Chip Stochastic CommunicationTudor Dumitras, Radu Marculescu. 10790-10795 [doi]
• An Integrated Approach for Improving Cache BehaviorGokhan Memik, Mahmut T. Kandemir, Alok N. Choudhary, Ismail Kadayif. 10796-10801 [doi]
• Rapid Configuration and Instruction Selection for an ASIP: A Case StudyNewton Cheung, Jörg Henkel, Sri Parameswaran. 10802-10809 [doi]
• Local Search for Boolean Relations on the Basis of Unit PropagationYakov Novikov. 10810-10815 [doi]
• Set Manipulation with Boolean Functional Vectors for Symbolic Reachability AnalysisAmit Goel, Randal E. Bryant. 10816-10821 [doi]
• Efficient Preimage Computation Using A Novel Success-Driven ATPGShuo Sheng, Michael S. Hsiao. 10822-10827 [doi]
• Using Formal Techniques to Debug the AMBA System-on-Chip Bus ProtocolAbhik Roychoudhury, Tulika Mitra, S. R. Karri. 10828-10833 [doi]
• Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions Avi Ziv. 10834-10841 [doi]
• Hot Topic Session: RF Design Technology for Highly Integrated Communication SystemsReimund Wittmann, Jürgen Hartung, Hans-Joachim Wassener, Günther Tränkle, Michael Schröter. 10842-10849 [doi]
• Power/Ground Mesh Area Optimization Using Multigrid-Based TechniqueKai Wang, Malgorzata Marek-Sadowska. 10850-10855 [doi]
• A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary TreesSteve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu. 10856-10861 [doi]
• Crosstalk Reduction in Area RoutingRyon M. Smey, Bill Swartz, Patrick H. Madden. 10862-10867 [doi]
• Area Fill Generation With Inherent Data Volume ReductionYu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng. 10868-10875 [doi]
• Transaction Based Design: Another Buzzword or the Solution to a Design Problem?Heinz-Joseph Schlebusch, Gary Smith, Donatella Sciuto, Daniel Gajski, Carsten Mielenz, Christopher K. Lennard, Frank Ghenassia, Stuart Swan, Joachim Kunkel. 10876-10879 [doi]
• Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other ApplicationsLintao Zhang, Sharad Malik. 10880-10885 [doi]
• Verification of Proofs of Unsatisfiability for CNF FormulasEvguenii I. Goldberg, Yakov Novikov. 10886-10891 [doi]
• A Circuit SAT Solver With Signal Correlation Guided LearningFeng Lu, Li-C. Wang, Kwang-Ting Cheng, Ric C.-Y. Huang. 10892-10897 [doi]
• Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate TraversalsGianpiero Cabodi, Sergio Nocco, Stefano Quer. 10898-10905 [doi]
• Generalized Data Transformations for Enhancing Cache BehaviorVictor De La Luz, Mahmut T. Kandemir, Ismail Kadayif, Ugur Sezer. 10906-10911 [doi]
• Software Streaming via Block StreamingPramote Kuacharoen, Vincent John Mooney, Vijay K. Madisetti. 10912-10917 [doi]
• Energy-Aware Adaptive Checkpointing in Embedded Real-Time SystemsYing Zhang, Krishnendu Chakrabarty. 10918-10925 [doi]
• Visualization and Resolution of Coding Conflicts in Asynchronous Circuit DesignAgnes Madalinski, Alexandre V. Bystrov, Victor Khomenko, Alexandre Yakovlev. 10926-10931 [doi]
• STG Optimisation in the Direct Mapping of Asynchronous Circuits Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev. 10932-10939 [doi]
• Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation IssuesLeandro Soares Indrusiak, Florian Lubitz, Ricardo Augusto da Luz Reis, Manfred Glesner. 10940-10945 [doi]
• Dynamic Tool Integration in Heterogeneous Computer NetworksWolfgang Müller 0003, Tim Schattkowsky, Heinz-Josef Eikerling, Jan Wegner. 10946-10953 [doi]
• Layered, Multi-Threaded, High-Level Performance DesignAndrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas. 10954-10959 [doi]
• A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution ProbabilitiesMarcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles. 10960-10965 [doi]
• Processor/Memory Co-Exploration on Multiple Abstraction LevelsGunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl. 10966-10973 [doi]
• Run-Time Management of Logic Resources on Reconfigurable SystemsManuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira. 10974-10979 [doi]
• Managing a Reconfigurable Processor in a General Purpose Workstation EnvironmentMichael Dales. 10980-10985 [doi]
• Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-ChipJean-Yves Mignolet, Vincent Nollet, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins. 10986-10993 [doi]
• RTL Test Pattern Generation for High Quality Loosely Deterministic BISTMarcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira. 10994-10999 [doi]
• A New Approach to Test Generation and Test Compaction for Scan CircuitsIrith Pomeranz, Sudhakar M. Reddy. 11000-11005 [doi]
• Fully Automatic Test Program Generation for Microprocessor CoresFulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero. 11006-11011 [doi]
• On the Characterization of Hard-to-Detect Bridging FaultsIrith Pomeranz, Sudhakar M. Reddy, Sandip Kundu. 11012-11019 [doi]
• The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method Yu-Min Lee, Charlie Chung-Ping Chen. 11020-11025 [doi]
• Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform MatchingZhong Wang, Jianwen Zhu. 11026-11031 [doi]
• A Fast Algorithm for the Layout Based Electro-Thermal SimulationMárta Rencz, Vladimir Székely, András Poppe. 11032-11037 [doi]
• Platform-Based Testbench GenerationRenate Henftling, Andreas Zinn, Matthias Bauer, Wolfgang Ecker, Martin Zambaldi. 11038-11045 [doi]
• Software Architectural Transformations: A New Approach to Low Energy Embedded SoftwareTat Kee Tan, Anand Raghunathan, Niraj K. Jha. 11046-11051 [doi]
• Dynamic Functional Unit Assignment for Low PowerSteve Haga, Natasha Reeves, Rajeev Barua, Diana Marculescu. 11052-11057 [doi]
• Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing EnergyMahmut T. Kandemir, Ibrahim Kolcu, Wei Zhang 0002. 11058-11063 [doi]
• Reducing Power Consumption for High-Associativity Data Caches in Embedded ProcessorsDan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau. 11064-11069 [doi]
• Layer Assignment echniques for Low Energy in Multi-Layered Memory OrganisationsErik Brockmeyer, Miguel Miranda, Henk Corporaal, Francky Catthoor. 11070-11075 [doi]
• Mesh Partitioning Approach to Energy Efficient Data LayoutSambuddhi Hettiaratchi, Peter Y. K. Cheung. 11076-11081 [doi]
• On-chip Stack Based Memory Organization for Low Power Embedded ArchitecturesMahesh Mamidipaka, Nikil D. Dutt. 11082-11089 [doi]
• Figure of Merit Based Selection of A/D ConvertersMartin Vogels, Georges G. E. Gielen. 11090-11091 [doi]
• XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode MachinesOliver Kraus, Martin Padeffke. 11092-11093 [doi]
• Multithreaded Synchronous Data Flow SimulationJohnson S. Kin, José Luis Pino. 11094-11095 [doi]
• PLFire: A Visualization Tool for Asynchronous Phased Logic DesignsKenneth Fazel, Mitchell A. Thornton, Robert B. Reese. 11096-11097 [doi]
• Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron ClusteringSimona Doboli, Gaurav Gothoskar, Alex Doboli. 11098-11099 [doi]
• Simulation and Analysis of Embedded DSP Systems Using MASIC MethodologyAbhijit K. Deb, Johnny Öberg, Axel Jantsch. 11100-11101 [doi]
• A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell DesignsJennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang. 11102-11103 [doi]
• Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area MigrationWonjoon Choi, Kia Bazargan. 11104-11105 [doi]
• LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building BlocksAlessandro Girardi, Sergio Bampi. 11106-11107 [doi]
• Symbolic Analysis of Nonlinear Analog CircuitsAlicia Manthe, Zhao Li, C.-J. Richard Shi, Kartikeya Mayaram. 11108-11109 [doi]
• Improved Time Domain Simulation of Optical Multimode Intrasystem InterconnectsJens Gerling, Oliver Stübbe, Jürgen Schrage, Gerd Mrozynski, Jürgen Teich. 11110-11111 [doi]
• A New Crosstalk Noise Model for DOMINO Logic CircuitsSeung Hoon Choi, Kaushik Roy. 11112-11113 [doi]
• Modeling Noise Transfer Characteristic of Dynamic Logic GatesLi Ding 0002, Pinaki Mazumder. 11114-11117 [doi]
• Heterogeneous Programmable Logic Block ArchitecturesAneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit. 11118-11119 [doi]
• An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture IntegrationJürgen Becker, Alexander Thomas, Martin Vorbach, Volker Baumgarten. 11120-11121 [doi]
• Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAsFernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans. 11122-11123 [doi]
• Mapping Applications to an FPFA TileMichèl A. J. Rosien, Yuanqing Guo, Gerard J. M. Smit, Thijs Krol. 11124-11125 [doi]
• Load Distribution with the Proximity Congestion Awareness in a Network on ChipErland Nilsson, Mikael Millberg, Johnny Öberg, Axel Jantsch. 11126-11127 [doi]
• Micro-Network for SoC: Implementation of a 32-Port SPIN networkAdrijean Andriahantenaina, Alain Greiner. 11128-11129 [doi]
• A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded SystemsAchim Rettberg, Mauro Cesar Zanella, Christophe Bobda, Thomas Lehmann. 11130-11131 [doi]
• Library Functions Timing Characterization for Source-Level AnalysisCarlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto. 11132-11133 [doi]
• G-MAC: An Application-Specific MAC/Co-Processor SynthesizerAlex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang. 11134-11135 [doi]
• Power Constrained High-Level Synthesis of Battery Powered Digital SystemsS. F. Nielsen, Jan Madsen. 11136-11137 [doi]
• PARLAK: Parametrized Lock Cache GeneratorBilge Saglam Akgul, Vincent John Mooney III. 11138-11139 [doi]
• A Secure Web-Based Framework for Electronic System Level DesignTom J. Kazmierski, Xing Q. Yang. 11140-11143 [doi]
• Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD ProcessorPieter Op de Beeck, C. Ghez, Erik Brockmeyer, Miguel Miranda, Francky Catthoor, Geert Deconinck. 11144-11145 [doi]
• Compiler Support for Reducing Leakage Energy ConsumptionWei Zhang 0002, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De. 11146-11147 [doi]
• An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion BatteriesPeng Rong, Massoud Pedram. 11148-11149 [doi]
• Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded SystemsJiong Luo, Li-Shiuan Peh, Niraj K. Jha. 11150-11151 [doi]
• Decomposition of Extended Finite State Machine for Low Power DesignMingHung Lee, TingTing Hwang, Shi-Yu Huang. 11152-11153 [doi]
• Equisolvability of Series vs. Controller s Topology in Synchronous Language EquationsNina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli. 11154-11155 [doi]
• Using RTL Statespace Information and State Encoding for Induction Based Property CheckingMarkus Wedler, Dominik Stoffel, Wolfgang Kunz. 11156-11157 [doi]
• Combining Simulation and Guided Traversal for the Verification of Concurrent SystemsEnric Pastor, Marco A. Peña. 11158-11159 [doi]
• Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled TechnologiesNaran Sirisantana, Kaushik Roy. 11160-11161 [doi]
• Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden CodesSteffen Tarnick. 11162-11163 [doi]
• Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity TreesPetros Drineas, Yiorgos Makris. 11164-11167 [doi]
• SAT-Based Techniques in System SynthesisChristian Haubelt, Jürgen Teich, Rainer Feldmann, Burkhard Monien. 11168-11169 [doi]
• Refinement of Mixed-Signal Systems with SystemCChristoph Grimm, Christian Meise, Wilhelm Heupke, Klaus Waldschmidt. 11170-11171 [doi]
• Polychrony for Refinement-Based DesignJean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta, Frederic Doucet. 11172-11173 [doi]
• Automatic Generation of Simulation Monitors from Quantitative Constraint FormulaXi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe. 11174-11175 [doi]
• Consequences of RAM Bitline Twisting for Test CoverageIvo Schanstra, A. J. van de Goor. 11176-11177 [doi]
• An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing SchemeFrancesco Corsi, Cristoforo Marzocca, Gianvito Matarrese. 11178-11179 [doi]
• Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPGHideyuki Ichihara, Tomoo Inoue. 11180-11181 [doi]
• Comparison of Test Pattern Decompression TechniquesOndrej Novák. 11182-11183 [doi]
• Evolutionary Optimization of Markov Sources for Pseudo Random Scan BISTIlia Polian, Bernd Becker, Sudhakar M. Reddy. 11184-11185 [doi]
• Test Data Compression Based on Output DependenceIrith Pomeranz, Sudhakar M. Reddy. 11186-11187 [doi]
• A Unified Approach for SOC Testing Using Test Data Compression and TAM OptimizationVikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty. 11188-11190 [doi]
• Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV LevelHiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo. 20002-20007 [doi]
• HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing ApplicationsHans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch. 20008-20013 [doi]
• Efficient Field Processing Cores in an Innovative Protocol Processor System-on-ChipGeorge Lykakis, N. Mouratidis, Kyriakos Vlachos, Nikos A. Nikolaou, Stylianos Perissakis, G. Sourdis, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Dionisios I. Reisis. 20014-20019 [doi]
• A Low Device Occupation IP to Implement Rijndael AlgorithmAlex Panato, Marcelo Barcelos, Ricardo Augusto da Luz Reis. 20020-20025 [doi]
• Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0Marco Caldari, Massimo Conti, Massimo Coppola, Stephane Curaba, Lorenzo Pieralisi, Claudio Turchetti. 20026-20031 [doi]
• System-Level Power Analysis Methodology Applied to the AMBA AHB BusMarco Caldari, Massimo Conti, Massimo Coppola, Paolo Crippa, Simone Orcioni, Lorenzo Pieralisi, Claudio Turchetti. 20032-20039 [doi]
• Designing System-Level Software Solutions for Open OS s on 3g Wireless HandsetsS. Glaeson, E. Petit. 20040 [doi]
• Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case StudyMonica Besana, Michele Borgatti. 20041-20044 [doi]
• Formal Methods for Integration of Automotive SoftwareMarek Jersak, Kai Richter, Rolf Ernst, Jörn-Christian Braam, Zheng-Yu Jiang, Fabian Wolf. 20045-20050 [doi]
• Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI InterconnectFrédéric Pétrot, Pascal Gomez. 20051-20056 [doi]
• Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental ResultsB. Nicolescu, Raoul Velazco. 20057-20063 [doi]
• Network Processing Challenges and an Experimental NPU PlatformPierre G. Paulin, Chuck Pilkington, Essaid Bensoudane. 20064-20069 [doi]
• SPIN: A Scalable, Packet Switched, On-Chip Micro-NetworkAdrijean Andriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, Cesar Albenes Zeferino. 20070-20073 [doi]
• NPSE: A High Performance Network Packet Search EngineNaresh Soni, Nick Richardson, Lun Bin Huang, Suresh Rajgopal, George Vlantis. 20074-20081 [doi]
• A Proposal for Transaction-Level Verification with Component Wrapper LanguageKoji Ara, Kei Suzuki. 20082-20087 [doi]
• Qualifying Precision of Abstract SystemC Models Using the SystemC Verification StandardFranco Carbognani, Christopher K. Lennard, C. Norris Ip, Allan Cochrane, Paul Bates. 20088-20094 [doi]
• A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip VerificationAli Sayinta, Gorkem Canverdi, Marc Pauwels, Amer Alshawa, Wim Dehaene. 20095-20100 [doi]
• SystemC-VHDL Co-Simulation and Synthesis in the HW DomainMassimo Bombana, Francesco Bruschi. 20101-20105 [doi]
• IPSIM: SystemC 3.0 Enhancements for Communication RefinementMarcello Coppola, Stephane Curaba, Miltos D. Grammatikakis, Giuseppe Maruccia. 20106-20111 [doi]
• Synthesis of Complex Control Structures from Behavioral SystemC ModelsFrancesco Bruschi, Fabrizio Ferrandi. 20112-20119 [doi]
• Exploring SW Performance Using SoC Transaction-Level ModelingImed Moussa, Thierry Grellier, Giang Nguyen. 20120-20125 [doi]
• A Flexible Object-Oriented Software Architecture for Smart Wireless Communication DevicesMarco Göltze. 20126-20131 [doi]
• Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC DesignYoungchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh. 20132-20137 [doi]
• Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and DeviceShinya Honda, Hiroaki Takada. 20138-20143 [doi]
• Interactive Ray Tracing on Reconfigurable SIMD MorphoSysHaitao Du, Marcos Sanchez-Elez, Nozar Tabrizi, Nader Bagherzadeh, Manuel L. Anido, Milagros Fernández. 20144-20149 [doi]
• Porting a Network Cryptographic Service to the RMC2000: A Case Study in Embedded Software DevelopmentStephen Jan, Paolo de Dios, Stephen A. Edwards. 20150-20157 [doi]
• Fast Evaluation of Protocol Processor Architectures for IPv6 RoutingJohan Lilius, Dragos Truscan, Seppo Virtanen. 20158-20163 [doi]
• A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL ModemsSilvia Brini, Doha Benjelloun, Fabien Castanier. 20164-20169 [doi]
• Transforming Structural Model to Runtime Model of Embedded Software with Real-Time ConstraintsSharath Kodase, Shige Wang, Kang G. Shin. 20170-20175 [doi]
• A Practical Approach for Bus Architecture Optimization at Transaction LevelOsamu Ogawa, Sylvain Bayon de Noyer, Pascal Chauvet, Katsuya Shinohara, Yoshiharu Watanabe, Hiroshi Niizuma, Takayuki Sasaki, Yuji Takai. 20176-20181 [doi]
• Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded ArchitectureGianluca Palermo, Cristina Silvano, Vittorio Zaccaria. 20182-20187 [doi]
• Estimation of Bus Performance for a Tuplespace in an Embedded ArchitectureNicola Drago, Franco Fummi, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino. 20188-20195 [doi]
• Defining Cost Functions for Robust IC Design and OptimizationÁrpád Bürmen, Janez Puhan, Tadej Tuma. 20196-20201 [doi]
• SoC Design and Test ConsiderationsMartin Schrader, Roderick McConnell. 20202-20207 [doi]
• A System to Validate and Certify Soft and Hard IPBernard Laurent, Thierry Karger. 20208-20213 [doi]
• SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy ChannelMarco Caldari, Massimo Conti, Paolo Crippa, Giuliano Marozzi, Fabio Di Gennaro, Simone Orcioni, Claudio Turchetti. 20214-20219 [doi]
• Set Top Box SoC Design Methodology at STMicroelectronicsFrançois Rémond, Pierre Bricaud. 20220-20223 [doi]
• Verification of a Complex SoC: The PRO3 Case-StudyFotis Andritsopoulos, C. Charopoulos, Gregory Doumenis, Fotis Karoubalis, Yannis Mitsos, F. Petreas, Ioanna Theologitou, Stylianos Perissakis, Dionisios I. Reisis. 20224-20231 [doi]
• System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive DomainLeonardo Mangeruca, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli, Andrea Pierantoni, Michele Pennese. 20232-20237 [doi]
• HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video DecoderMatjaz Verderber, Andrej Zemva, Damjan Lampret. 20238-20243 [doi]
• Reconfigurable Signal Processing in Wireless TerminalsJürgen Helmschmidt, Eberhard Schüler, Prashant Rao, Sergio Rossi, Serge di Matteo, Rainer Bonitz. 20244-20249 [doi]
• A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP IntegrationAdel Baganne, Imed Bennour, Mehrez Elmarzougui, Riadh Gaiech, Eric Martin. 20250-20255 [doi]
• Comparing Analytical Modeling with Simulation for Network Processors: A Case StudyMatthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer. 20256-20261 [doi]
• A Solution for Hardware Emulation of Non Volatile Memory MacrocellsAlessandro Pirola. 20262-20267 [doi]
• Bluetooth Transceiver Design with VHDL-AMSRami Ahola, Daniel Wallner, Marius Sida. 20268-20273 [doi]
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• Automatic Behavioural Model Calibration for Efficient PLL System VerificationAyman Mounir, Ahmed Mostafa, Maged Fikry. 20280-20285 [doi]
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