Robert B. Reese - researchr alias

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Viewing Publication 1 - 18 from 18

2015

2014

Setting the stage for CE2016: A revised body of knowledgeEric Durant, John Impagliazzo, Susan Conry, Robert B. Reese, Mitchell A. Thornton, Herman Lam, Victor P. Nelson. mcs 2014: 1-4 [doi]

2012

Uncle - An RTL Approach to Asynchronous DesignRobert B. Reese, Scott C. Smith, Mitchell A. Thornton. async 2012: 65-72 [doi]

2007

Finite State Machine Datapath Design, Optimization, and ImplementationJustin Davis, Robert B. Reese. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, 2007. [doi]

2006

Introduction to Logic Synthesis using Verilog HDLRobert B. Reese, Mitchell A. Thornton. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, 2006. [doi]

2005

A Coarse-Grain Phased Logic CPURobert B. Reese, Mitchell A. Thornton, Cherrice Traver. TC, 54(7):788-799, 2005. [doi]

Early evaluation for performance enhancement in phased logicRobert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger. tcad, 24(4):532-550, 2005. [doi]

2004

Performance enhancement in phased logic circuits using automatic slack-matching buffer insertionKenneth Fazel, Lun Li, Mitchell A. Thornton, Robert B. Reese, Cherrice Traver. glvlsi 2004: 413-416 [doi]

2003

PLFire: A Visualization Tool for Asynchronous Phased Logic DesignsKenneth Fazel, Mitchell A. Thornton, Robert B. Reese. date 2003: 11096-11097 [doi]

A Fine-Grain Phased Logic CPURobert B. Reese, Mitchell A. Thornton, Cherrice Traver. isvlsi 2003: 70-79 [doi]

A Coarse-Grain Phased Logic CPURobert B. Reese, Mitchell A. Thornton, Cherrice Traver. async 2003: 2-13 [doi]

2002

Generalized Early Evaluation in Self-Timed CircuitsMitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver. date 2002: 255-259 [doi]

2001

Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early EvaluationRobert B. Reese, Mitchell A. Thornton, Cherrice Traver. iccd 2001: 18-23

2000

OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the InternetHemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha Chandrakasan. iccd 2000: 567-570 [doi]

1999

User-configurable experimental design flows on the web: the ISCAS 99 experimentsHemang Lavana, Franc Brglez, Robert B. Reese. iscas 1999: 440-443 [doi]

1997

Developing and Distributing Component-Level VHDL ModelsJ. Scott Calhoun, Vijay K. Madisetti, Robert B. Reese, Thomas Egolf. vlsisp, 15(1-2):111-126, 1997. [doi]

1993

A Comparison of Synchronous and Asynchronous FSMD DesignsRichard Auletta, Robert B. Reese, Cherrice Traver. iccd 1993: 178-182

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