Abstract is missing.
- Statistical Analysis and Optimization of Asynchronous Digital CircuitsTsung-Te Liu, Jan M. Rabaey. 1-8 [doi]
- Performance Bounds of Asynchronous Circuits with Mode-Based Conditional BehaviorMehrdad Najibi, Peter A. Beerel. 9-16 [doi]
- Adapting Asynchronous Circuits to Operating Conditions by Logic ParametrisationAndrey Mokhov, Danil Sokolov, Alex Yakovlev. 17-24 [doi]
- A Digital Neurosynaptic Core Using Event-Driven QDI CircuitsNabil Imam, Filipp Akopyan, John V. Arthur, Paul Merolla, Rajit Manohar, Dharmendra S. Modha. 25-32 [doi]
- A Low Power Asynchronous GPS Baseband ProcessorBenjamin Tang, Stephen Longfield Jr., Sunil A. Bhave, Rajit Manohar. 33-40 [doi]
- High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search MechanismNaoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu. 41-48 [doi]
- An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data RecoveryJim D. Garside, Stephen B. Furber, Steve Temple, David M. Clark, Luis A. Plana. 49-56 [doi]
- A Fast Hierarchical Approach to Resource Sharing in Pipelined Asynchronous SystemsJohn Hansen, Montek Singh. 57-64 [doi]
- Uncle - An RTL Approach to Asynchronous DesignRobert B. Reese, Scott C. Smith, Mitchell A. Thornton. 65-72 [doi]
- A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous CircuitsYvain Thonnart, Edith Beigné, Pascal Vivet. 73-80 [doi]
- Ultra Low Power Booth Multiplier Using Asynchronous LogicJiaoyan Chen, Emanuel M. Popovici, Dilip P. Vasudevan, Michel P. Schellekens. 81-88 [doi]
- An Asynchronous Floating-Point MultiplierBasit Riaz Sheikh, Rajit Manohar. 89-96 [doi]
- An Asynchronous Divider ImplementationNavaneeth Jamadagni, Jo C. Ebergen. 97-104 [doi]
- Tiempo Asynchronous Circuits System Verilog Modeling LanguageMarc Renaudin, Alain Fonkoua. 105-112 [doi]
- Introduction to Octasic Asynchronous Processor TechnologyMichel Laurence. 113-117 [doi]
- DVFS Based on Voltage Dithering and Clock Scheduling for GALS SystemsManoj Kumar Yadav, Mario R. Casu, Maurizio Zamboni. 118-125 [doi]
- Performance Analysis of GALS Datalink Based on Pausible ClockingXin Fan, Milos Krstic, Eckhard Grass. 126-133 [doi]
- PID (Partial Inversion Data): An M-of-N Level-Encoded Transition Signaling Protocol for Asynchronous Global CommunicationMarco Cannizzaro, Luciano Lavagno. 134-141 [doi]
- Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event EffectsJulian J. H. Pontes, Ney Calazans, Pascal Vivet. 142-149 [doi]
- Self Synchronous Circuits for Error Robust Operation in Sub-100nm ProcessesBenjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada. 150-157 [doi]