Dilip P. Vasudevan - researchr alias

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Viewing Publication 1 - 18 from 18

2020

Language Support for Navigating Architecture Design in Closed FormWeilong Cui, Georgios Tzimpragos, Yu Tao, Joseph McMahan, Deeksha Dangwal, Nestan Tsiskaridze, George Michelogiannakis, Dilip P. Vasudevan, Timothy Sherwood. jetc, 16(1), 2020. [doi]

2019

PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and ExperimentsDilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf. ispass 2019: 139-140 [doi]

3D photonics as enabling technology for deep 3D DRAM stackingSebastian Werner, Pouya Fotouhi, Xian Xiao, Marjan Fariborz, S. J. Ben Yoo, George Michelogiannakis, Dilip P. Vasudevan. memsys 2019: 206-221 [doi]

2017

CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devicesDilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf. NANOARCH 2017: 117-118 [doi]

Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging TechnologiesDilip P. Vasudevan, Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf. supercomputer 2017: 115-123 [doi]

2015

10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated ArchitectureAndrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati. sigarch, 43(3):2-9, 2015. [doi]

The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short DataDilip P. Vasudevan, Andrew A. Chien. glvlsi 2015: 103-106 [doi]

2012

Ultra Low Power Booth Multiplier Using Asynchronous LogicJiaoyan Chen, Emanuel M. Popovici, Dilip P. Vasudevan, Michel P. Schellekens. async 2012: 81-88 [doi]

Ultra Low Power Asynchronous Charge Sharing LogicJiaoyan Chen, Dilip P. Vasudevan, Michel P. Schellekens, Emanuel M. Popovici. jolpe, 8(4):526-534, 2012. [doi]

2011

Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional AdderJiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens. dsd 2011: 301-308 [doi]

Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testingXiaodong Wang, Dilip P. Vasudevan, Hsien-Hsin S. Lee. 3dic 2012: 1-8 [doi]

2010

2008

A Partial Scan Based Test Generation for Asynchronous CircuitsDilip P. Vasudevan, Aristides Efthymiou. ddecs 2008: 186-189 [doi]

2007

Self-Checking Carry-Select Adder Design Based on Two-Rail EncodingDilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson. tcas, 54-I(12):2696-2705, 2007. [doi]

2006

Reversible-logic design with online testabilityDilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson. tim, 55(2):406-414, 2006. [doi]

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