Abstract is missing.
- Digital Microfluidic Biochips: Towards Functional Diversity, More than Moore, and Cyberphysical IntegrationKrishnendu Chakrabarty. 1 [doi]
- Efficient Test Application for Rapid Multi-Temperature TestingNima Aghaee, Zebo Peng, Petru Eles. 3-8 [doi]
- Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC ExecutionDimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar. 9-14 [doi]
- DRAM based Intrinsic Physical Unclonable Functions for System Level SecurityFatemeh Tehranipoor, Nima Karimina, Kan Xiao, John A. Chandy. 15-20 [doi]
- An Effective TSV Self-Repair Scheme for 3D-Stacked ICsSongwei Pei, Jingdong Zhang, Yu Jin, Song Jin, Jun Liu, Weizhi Xu. 21-26 [doi]
- Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICsTiantao Lu, Ankur Srivastava. 27-32 [doi]
- Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard CellsTiansong Cui, Bowen Chen, Yanzhi Wang, Shahin Nazarian, Massoud Pedram. 33-38 [doi]
- Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis OptimizationSandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon. 39-44 [doi]
- A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold CircuitsMarco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky. 45-50 [doi]
- Design of Approximate Unsigned Integer Non-restoring Divider for Inexact ComputingLinbin Chen, Jie Han, Weiqiang Liu, Fabrizio Lombardi. 51-56 [doi]
- Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability ModelsDimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic. 57-62 [doi]
- Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore ArchitecturesSai Vineel Reddy Chittamuru, Srinivas Desai, Sudeep Pasricha. 63-68 [doi]
- A High-Speed Robust NVM-TCAM Design Using Body Bias FeedbackBonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li, Weisheng Zhao, Pierre Chor-Fung Chia. 69-74 [doi]
- Characterizing the Activity Factor in NBTI Aging Models for Embedded CoresYukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino. 75-78 [doi]
- Improving Lifetime of Multicore Soft Real-Time Systems through Global Utilization ControlYue Ma, Thidapat Chantem, Xiaobo Sharon Hu, Robert P. Dick. 79-82 [doi]
- Directed Self-Assembly Based Cut Mask Optimization for Unidirectional DesignJiaojiao Ou, Bei Yu, Jhih-Rong Gao, David Z. Pan, Moshe Preil, Azat Latypov. 83-86 [doi]
- Skew Bounded Buffer Tree Resynthesis For Clock Power OptimizationSubhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet. 87-90 [doi]
- Novel Designs of Embedded Hybrid Cells for High Performance Memory CircuitsFabrizio Lombardi, Wei Wei, Kazuteru Namba. 91-94 [doi]
- cell SRAM Using FinFETBhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi. 95-98 [doi]
- Statistically Validating the Impact of Process Variations on Analog and Mixed Signal DesignsIbtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar. 99-102 [doi]
- The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short DataDilip P. Vasudevan, Andrew A. Chien. 103-106 [doi]
- Reduced-latency LLR-based SC List Decoder for Polar CodesBo Yuan, Keshab K. Parhi. 107-110 [doi]
- Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAsMonther Abusultan, Sunil P. Khatri. 111-114 [doi]
- Phase-based Cache Locking for Embedded SystemsTosiron Adegbija, Ann Gordon-Ross. 115-120 [doi]
- A Multilayered Design Approach for Efficient Hybrid 3D Photonics Network-on-chipDharanidhar Dang, Biplab Patra, Rabi N. Mahapatra. 121-126 [doi]
- Analyzing the Dark Silicon Phenomenon in a Many-Core Chip Multi-Processor under Deeply-Scaled Process TechnologiesAlireza Shafaei Bejestan, Yanzhi Wang, Srikanth Ramadurgam, Yuankun Xue, Paul Bogdan, Massoud Pedram. 127-132 [doi]
- Small-World Network Enabled Energy Efficient and Robust 3D NoC ArchitecturesSourav Das, DongJin Lee, Dae-Hyun Kim, Partha Pratim Pande. 133-138 [doi]
- A Dynamically Reconfigurable RF NoC for Many-CoreAlexandre Briere, Julien Denoulet, Andréa Pinna, Bertrand Granado, François Pêcheux, Eren Unlu, Yves Louët, Christophe Moy. 139-144 [doi]
- Computational Thinking Meets Design Thinking: Technology and Arts CollaborationsErik Brunvand. 145 [doi]
- Graphene Neural Sensors for Next Generation In Vivo Imaging and OptogeneticsZhenqiang Jack Ma. 147 [doi]
- Online and Operand-Aware Detection of Failures Utilizing False Alarm VectorsAmir Yazdanbakhsh, David J. Palframan, Azadeh Davoodi, Nam Sung Kim, Mikko H. Lipasti. 149-154 [doi]
- Speed Binning Using Machine Learning And On-chip Slack SensorsMehdi Sadi, Mark Tehranipoor, Xiaoxiao Wang, LeRoy Winemberg. 155-160 [doi]
- Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled SystemsMichail Mavropoulos, Georgios Keramidas, Grigorios Adamopoulos, Dimitris Nikolos. 161-166 [doi]
- Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level SynthesisAnirban Sengupta, Saumya Bhadauria. 167-172 [doi]
- Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense AmplifiersSamira Ataei, James E. Stine. 173-178 [doi]
- MSCS: Multi-hop Segmented Circuit SwitchingDonald Kline Jr., Kai Wang, Rami G. Melhem, Alex K. Jones. 179-184 [doi]
- EDA Challenges for Memristor-Crossbar based Neuromorphic ComputingBeiye Liu, Wei Wen, Yiran Chen, Xin Li, Chi-Ruo Wu, Tsung-Yi Ho. 185-188 [doi]
- Energy Efficient RRAM Spiking Neural Network for Real Time ClassificationYu Wang, Tianqi Tang, Lixue Xia, Boxun Li, Peng Gu, Huazhong Yang, Hai Li, Yuan Xie 0001. 189-194 [doi]
- On-chip Sparse Learning with Resistive Cross-point Array ArchitectureShimeng Yu, Yu Cao. 195-197 [doi]
- Origami: A Convolutional Network AcceleratorLukas Cavigelli, David Gschwend, Christoph Mayer, Samuel Willi, Beat Muheim, Luca Benini. 199-204 [doi]
- Restricted Clustered Neural Network for Storing Real DataRobin Danilo, Philippe Coussy, Laura Conde-Canencia, Vincent Gripon, Warren J. Gross. 205-210 [doi]
- NeuroDSP Accelerator for Face Detection ApplicationMichel Paindavoine, Olivier Boisard, Alexandre Carbon, Jean-Marc Philippe, Olivier Brousse. 211-215 [doi]
- Space Oblivious Compression: Power Reduction for Non-Volatile Main MemoriesYong Li, Haifeng Xu, Rami G. Melhem, Alex K. Jones. 217-220 [doi]
- Flip-Mirror-Rotate: An Architecture for Bit-write Reduction and Wear Leveling in Non-volatile MemoriesPoovaiah M. Palangappa, Kartik Mohanram. 221-224 [doi]
- Fine-Grained Voltage Boosting for Improving Yield in Near-Threshold Many-Core ProcessorsJoonho Kong, Arslan Munir, Farinaz Koushanfar. 225-228 [doi]
- Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs AnalysisGeorgios Zervakis, Kostas Tsoumanis, Sotirios Xydis, Nicholas Axelos, Kiamal Z. Pekmestzi. 229-232 [doi]
- A SystemC Platform for Signal Transduction Modelling and Simulation in Systems BiologyRosario Distefano, Franco Fummi, Carlo Laudanna, Nicola Bombieri, Rosalba Giugno. 233-236 [doi]
- Yield-aware Performance-Cost Characterization for Multi-Core SIMTSeyyed Hasan Mozafari, Brett H. Meyer, Kevin Skadron. 237-240 [doi]
- An Efficient Approach to Sample On-Chip Power SuppliesLuke Murray, Sunil P. Khatri. 241-244 [doi]
- Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC DecodingThomas Marconi, Sorin Cotofana. 245-248 [doi]
- Dynamic Power Reduction Techniques in On-Chip Photonic InterconnectsBrian Neel, Matthew Kennedy, Avinash Karanth Kodi. 249-252 [doi]
- Design and Characterization of Analog-to-Digital Converters using Graphene P-N JunctionsRoberto Giorgio Rizzo, Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino. 253-258 [doi]
- A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM)Pilin Junsangsri, Fabrizio Lombardi, Jie Han. 259-264 [doi]
- Characterization of SWCNT Bundle Based VLSI Interconnect with Self-heating Induced ScatteringsK. M. Mohsin, Ashok Srivastava. 265-270 [doi]
- A Novel True Random Number Generator Design Leveraging Emerging Memristor TechnologyYandan Wang, Wei Wen, Hai Li, Miao Hu. 271-276 [doi]
- TFET-based Operational Transconductance Amplifier Design for CNN SystemsQiuwen Lou, Indranil Palit, András Horváth, Xiaobo Sharon Hu, Michael T. Niemier, Joseph Nahas. 277-282 [doi]
- Clock Skew Scheduling in the Presence of Heavily Gated Clock NetworksWeicheng Liu, Emre Salman, Can Sitik, Baris Taskin. 283-288 [doi]
- Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-LineWei Ye, Bei Yu, David Z. Pan, Yongchan Ban, Lars Liebmann. 289-294 [doi]
- Inevitability of Phase-locking in a Charge Pump Phase Lock Loop using Deductive VerificationHafiz ul Asad, Kevin D. Jones. 295-300 [doi]
- A Novel Static D-Flip-Flop Topology for Low Swing ClockingMallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin. 301-306 [doi]
- Voltage-Boosted SynchronizersYaoqiang Li, Pierce I.-Jen Chuang, Andrew A. Kennings, Manoj Sachdev. 307-312 [doi]
- Recent Advances in Brain-controlled Prosthetics for Paralysis: Friday KeynoteAndrew Schwartz. 313 [doi]
- Formal Analysis Provides Parameters for Guiding Hyperoxidation in Bacteria using Phototoxic ProteinsQinsi Wang, Natasa Miskov-Zivanov, Cheryl Telmer, Edmund M. Clarke. 315-320 [doi]
- Design Automation for Biological Models: A Pipeline that Incorporates Spatial and Molecular ComplexityDevin P. Sullivan, Rohan Arepally, Robert F. Murphy, José Juan Tapia, James R. Faeder, Markus Dittrich, Jacob Czech. 321-323 [doi]
- Mammalian Synthetic Gene NetworksJason Lohmueller. 325-326 [doi]
- Automation of Biological Model Learning, Design and AnalysisNatasa Miskov-Zivanov. 327-329 [doi]
- On the Functions Realized by Stochastic Computing CircuitsArmin Alaghi, John P. Hayes. 331-336 [doi]
- ApproxMA: Approximate Memory Access for Dynamic Precision ScalingYe Tian, Qian Zhang, Ting Wang, Feng Yuan, Qiang Xu. 337-342 [doi]
- A Comparative Review and Evaluation of Approximate AddersHonglan Jiang, Jie Han, Fabrizio Lombardi. 343-348 [doi]
- Minimizing Error of Stochastic Computation through Linear TransformationYi Wu, Chen Wang, Weikang Qian. 349-354 [doi]
- Experimental Validation of a Faithful Binary Circuit ModelRobert Najvirt, Ulrich Schmid, Michael Hofbauer, Matthias Függer, Thomas Nowak, Kurt Schweiger. 355-360 [doi]
- Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay ModelJiani Xie, C. Y. Roger Chen. 361-366 [doi]
- A Novel Framework for Temperature Dependence Aware Clock Skew SchedulingMineo Kaneko. 367-372 [doi]
- Dynamic Task Priority Scaling for Thermal Management of Multi-core Processors with Heavy WorkloadAli Akbari, Saadat Pour-Mozafari, Hamid Noori, Farhad Mehdipour. 373-378 [doi]
- Reinforcement Learning for Thermal-aware Many-core Task AllocationShiting (Justin) Lu, Russell Tessier, Wayne P. Burleson. 379-384 [doi]
- Revisiting Dynamic Thermal Management Exploiting Inverse Thermal DependenceKatayoun Neshatpour, Houman Homayoun, Amin Khajeh, Wayne Burleson. 385-390 [doi]
- Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx MemoryMohammad Hossein Hajkazemi, Michael Chorney, Reyhaneh Jabbarvand Behrouz, Mohammad Khavari Tavana, Houman Homayoun. 391-396 [doi]
- Optimizing VMIN of ROM Arrays Without Loss of Noise MarginAvijit Chakraborty, D. M. H. Walker. 397-402 [doi]