Laurent Masse-Navette - researchr alias

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Viewing Publication 1 - 5 from 5

2019

Timing-Driven and Placement-Aware Multibit Register CompositionIoannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery. tcad, 38(8):1501-1514, 2019. [doi]

2017

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulationIoannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David Chinnery. dac 2017: [doi]

2015

Skew Bounded Buffer Tree Resynthesis For Clock Power OptimizationSubhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet. glvlsi 2015: 87-90 [doi]

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing ClosureSubhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan. tcad, 34(4):589-602, 2015. [doi]

2014

Clock tree resynthesis for multi-corner multi-mode timing closureSubhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan. ispd 2014: 69-76 [doi]

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