Abstract is missing.
- Hardware cyber securitySerge Leef. 1-2 [doi]
- Cell density-driven detailed placement with displacement constraintWing-Kai Chow, Jian Kuang 0001, Xu He, Wenzan Cai, Evangeline F. Y. Young. 3-10 [doi]
- MIP-based detailed placer for mixed-size circuitsShuai Li, Cheng-Kok Koh. 11-18 [doi]
- A study on unroutable placement recognitionWen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang. 19-26 [doi]
- Integrated structured placement design methodology in place and route flowAnand Arunachalam. 27-28 [doi]
- Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraintsYilin Zhang, David Z. Pan. 29-36 [doi]
- A fast algorithm for rectilinear steiner trees with length restrictions on obstaclesStephan Held, Sophie Theresa Spirkl. 37-44 [doi]
- FPGA place & route challengesRajat Aggarwal. 45-46 [doi]
- Placement-driven partitioning for congestion mitigation in monolithic 3D IC designsShreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim. 47-54 [doi]
- Coupling-aware force driven placement of TSVs and shields in 3D-IC layoutsCaleb Serafy, Ankur Srivastava. 55-62 [doi]
- 3DIC system design impact, challenge and solutionsWilliam Wu Shen. 63-64 [doi]
- Physical design and FinFETsRobert C. Aitken, Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra. 65-68 [doi]
- Clock tree resynthesis for multi-corner multi-mode timing closureSubhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan. 69-76 [doi]
- Power optimization for clock network with clock gate cloning and flip-flop mergingShih-Chuan Lo, Chih-Cheng Hsu, Mark Po-Hung Lin. 77-84 [doi]
- Current density aware power switch placement algorithm for power gating designsJai-Ming Lin, Che-Chun Lin, Zong-Wei Syu, Chih-Chung Tsai, Kevin Huang. 85-92 [doi]
- Incremental transient simulation of power gridChia-Tung Ho, Yu-Min Lee, Shu-Han Wei, Liang-Chia Cheng. 93-100 [doi]
- Self-aligned double patterning aware pin access and standard cell layout co-optimizationXiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan. 101-108 [doi]
- A highly-efficient row-structure stencil planning approach for e-beam lithography with overlapped charactersJian Kuang 0001, Evangeline F. Y. Young. 109-116 [doi]
- Carbon nanotube computer: transforming scientific discoveries into working systemsSubhasish Mitra. 117-118 [doi]
- Making a difference in EDA: a thank you to Bryan Preas for his contributions to the professionMichael J. Lorenzetti. 119-120 [doi]
- From design to design automationJason Cong. 121-126 [doi]
- Interconnect length estimation in VLSI designs: a retrospectiveMassoud Pedram. 127-128 [doi]
- Bryan Preas: broad contributions to system engineering in the 2000'sScott Elrod. 129-130 [doi]
- Smart matter systems, an introduction through examplesBryan Preas. 131-132 [doi]
- Reliability-driven chip-level design for high-frequency digital microfluidic biochipsShang-Tsung Yu, Sheng-Han Yeh, Tsung-Yi Ho. 133-140 [doi]
- Design synthesis and optimization for automotive embedded systemsQi Zhu, Peng Deng. 141-148 [doi]
- Opportunities in power distribution network system optimization: from EDA perspectiveGi-Joon Nam, Sani R. Nassif. 149-150 [doi]
- Indoor localization technology and algorithm issuesFan Ye. 151-152 [doi]
- TAU 2014 contest on removing common path pessimism during timing analysisJin Hu, Debjit Sinha, Igor Keller. 153-160 [doi]
- ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placementVladimir Yutsis, Ismail Bustany, David G. Chinnery, Joseph R. Shinnerl, Wen-Hao Liu. 161-168 [doi]