Abstract is missing.
- TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCsAmin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran. [doi]
- Bandwidth Optimization Through On-Chip Memory Restructuring for HLSJason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou. [doi]
- Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and OverproductionYang Xie, Ankur Srivastava. [doi]
- Making DRAM Stronger Against Row HammeringMungyu Son, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo. [doi]
- Improving Performance and Lifetime of Large-Page NAND Storages Using Erase-Free Subpage ProgrammingMyungsuk Kim, Jaehoon Lee, Sungjin Lee, Jisung Park, Jihong Kim. [doi]
- Secure Information Flow Verification with Mutable Dependent TypesAndrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh. [doi]
- Power-aware Performance Tuning of GPU Applications Through MicrobenchmarkingNicola Bombieri, Federico Busato, Franco Fummi. [doi]
- Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging EffectJiangyuan Gu, Shouyi Yin, Shaojun Wei. [doi]
- Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAMShouyi Yin, Zhicong Xie, Shaojun Wei. [doi]
- Deep3: Leveraging Three Levels of Parallelism for Efficient Deep LearningBita Darvish Rouhani, Azalia Mirhoseini, Farinaz Koushanfar. [doi]
- Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel StorageChunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann. [doi]
- InCheck: An In-application Recovery Scheme for Soft ErrorsMoslem Didehban, Sai Ram Dheeraj Lokam, Aviral Shrivastava. [doi]
- Closing the Accuracy Gap of Static Performance Analysis of Asynchronous CircuitsCheng-Yu Shih, Chun-Hong Shih, Jie-Hong R. Jiangs. [doi]
- Network Synthesis for Database Processing UnitsAndrea Lottarini, Stephen A. Edwards, Kenneth A. Ross, Martha A. Kim. [doi]
- Fast and Energy-Efficient Digital Filters for Signal Conditioning in Low-Power MicrocontrollersCarlos Moreno, Sebastian Fischmeister. [doi]
- A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural NetworksHyeon Uk Sim, Jongeun Lee. [doi]
- RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural NetworksAayush Ankit, Abhronil Sengupta, Priyadarshini Panda, Kaushik Roy 0001. [doi]
- Test Methodology for Dual-rail Asynchronous CircuitsKuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li. [doi]
- Optimizing Memory Efficiency for Convolution Kernels on Kepler GPUsXiaoming Chen, Jianxu Chen, Danny Z. Chen, Xiaobo Sharon Hu. [doi]
- Cryo-CMOS Electronic Control for Scalable Quantum Computing: InvitedFabio Sebastiano, Harald Homulle, Bishnu Patra, Rosario M. Incandela, Jeroen P. G. van Dijk, Lin Song, Masoud Babaie, Andrei Vladimirescu, Edoardo Charbon. [doi]
- Group Scissor: Scaling Neuromorphic Computing Design to Large Neural NetworksYandan Wang, Wei Wen, Beiye Liu, Donald M. Chiarulli, Hai (Helen) Li. [doi]
- Linear Periodically Time-Varying (LPTV) Circuits Enable New Radio Architectures for Emerging Wireless Communication Paradigms: Extended Abstract: InvitedNegar Reiskarimian, Linxiao Zhang, Harish Krishnaswamy. [doi]
- Task Mapping on SMART NoC: Contention Matters, Not the DistanceLei Yang 0018, Weichen Liu, Peng Chen, Nan Guan, Mengquan Li. [doi]
- Dealing with Uncertainties in Analog/Mixed-Signal Systems: InvitedChristoph Grimm 0001, Michael Rathmair. [doi]
- Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant MultithreadingManish Gupta, Daniel Lowell, John Kalamatianos, Steven Raasch, Vilas Sridharan, Dean M. Tullsen, Rajesh K. Gupta. [doi]
- Hierarchical Reversible Logic Synthesis Using LUTsMathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli. [doi]
- Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAsXuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, Jason Cong. [doi]
- LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip VariationsSong Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato. [doi]
- Real-Time Multi-Scale Pedestrian Detection for Driver Assistance SystemsMaryam Hemmati, Morteza Biglari-Abhari, Smaïl Niar, Stevan Berber. [doi]
- Adaptive Thermal Management for 3D ICs with Stacked DRAM CachesDawei Li, Kaicheng Zhang, Akhil Guliani, Seda Ogrenci Memik. [doi]
- Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock ManagementTianyu Jia, Russ Joseph, Jie Gu. [doi]
- A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face AlignmentQiang Wang, Leibo Liu, Wenping Zhu, Huiyu Mo, Chenchen Deng, Shaojun Wei. [doi]
- Hierarchical Dataflow Modeling of Iterative ApplicationsHyesun Hong, Hyunok Oh, Soonhoi Ha. [doi]
- 3 Channel Dependency-Based Power Model for Mobile AMOLED DisplaysSeongwoo Hong, Suk Won Kim, Young-Jin Kim. [doi]
- A Clock Skewing Strategy to Reduce Power and Area of ASIC CircuitsNiranjan Kulkarni, Aykut Dengi, Sarma B. K. Vrudhula. [doi]
- Co-training of Feature Extraction and Classification using Partitioned Convolutional Neural NetworksWei-Yu Tsai, Jinhang Choi, Tulika Parija, Priyanka Gomatam, Chita R. Das, John Sampson, Vijaykrishnan Narayanan. [doi]
- Multi-variable Dynamic Power Management for the GPU SubsystemPietro Mercati, Raid Ayoub, Michael Kishinevsky, Eric Samson, Marc Beuchat, Francesco Paterna, Tajana Simunic Rosing. [doi]
- Cooperative DVFS for energy-efficient HEVC decoding on embedded CPU-GPU architectureFan Gong, Lei Ju, Deshan Zhang, Mengying Zhao, Zhiping Jia. [doi]
- Learning to Produce Direct Tests for Security Verification Using Constrained Process DiscoveryKuo-Kai Hsieh, Li-C. Wang, Wen Chen, Jayanta Bhadra. [doi]
- Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered NetworksFedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich. [doi]
- Statistical Pattern Based Modeling of GPU Memory Access StreamsReena Panda, Xinnian Zheng, Jiajun Wang, Andreas Gerstlauer, Lizy K. John. [doi]
- Power and Area Efficient Hold Time Fixing by Free Metal Segment AllocationWei-Lun Chiu, Iris Hui-Ru Jiang, Chien Pang Lu, Yu-Tung Chang. [doi]
- Energy and Performance Trade-off in Nanophotonic Interconnects using Coding TechniquesCedric Killian, Daniel Chillet, Sébastien Le Beux, Van-Dung Pham, Olivier Sentieys, Ian O'Connor. [doi]
- Accelerator Design for Deep Learning Training: Extended Abstract: InvitedAnkur Agrawal, Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Jinwook Oh, Sunil Shukla, Viji Srinivasan, Swagath Venkataramani, Wei Zhang. [doi]
- LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAsLove Singhal, Mahesh A. Iyer, Saurabh N. Adya. [doi]
- Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias TechniqueTianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang. [doi]
- A Spectral Graph Sparsification Approach to Scalable Vectorless Power Grid Integrity VerificationZhiqiang Zhao, Zhuo Feng. [doi]
- Towards Full-System Energy-Accuracy Tradeoffs: A Case Study of An Approximate Smart Camera SystemArnab Raha, Vijay Raghunathan. [doi]
- Dadu: Accelerating Inverse Kinematics for High-DOF RobotsShiqi Lian, Yinhe Han, Ying Wang, Yungang Bao, Hang Xiao, Xiaowei Li, Ninghui Sun. [doi]
- Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating ApproachChun-Hao Lai, Jishen Zhao, Chia-Lin Yang. [doi]
- A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and ReliabilityYang Zhang, Dan Feng, Jingning Liu, Wei Tong, Bing Wu, Caihua Fang. [doi]
- Optimized Design of a Human Intranet NetworkAli Moin, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli, Jan M. Rabaey. [doi]
- A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: InvitedJian-Ping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy 0001, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami. [doi]
- Estimation of Safe Sensor Measurements of Autonomous System Under AttackRaj Gautam Dutta, Xiaolong Guo, Teng Zhang, Kevin A. Kwiat, Charles A. Kamhoua, Laurent Njilla, Yier Jin. [doi]
- On Quality Trade-off Control for Approximate Computing Using Iterative TrainingChengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang, Li Jiang. [doi]
- Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault AttackMeng Li, Liangzhen Lai, Vikas Chandra, David Z. Pan. [doi]
- Maximizing Forward Progress with Cache-aware Backup for Self-powered Non-volatile ProcessorsJing Li, Mengying Zhao, Lei Ju, Chun Jason Xue, Zhiping Jia. [doi]
- HyCUBE: A CGRA with Reconfigurable Single-cycle Multi-hop InterconnectManupa Karunaratne, Aditi Kulkarni Mohite, Tulika Mitra, Li-Shiuan Peh. [doi]
- Coupled circuit/EM simulation for radio frequency circuitsKai Bittner, Hans Georg Brachtendorf, Wim Schoenmaker, Pascal Reynier. [doi]
- A Kernel Decomposition Architecture for Binary-weight Convolutional Neural NetworksHyeonuk Kim, Jaehyeong Sim, YeongJae Choi, Lee-Sup Kim. [doi]
- Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network DesignGengjie Chen, Jian Kuang 0001, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu. [doi]
- Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAsQingcheng Xiao, Yun Liang, Liqiang Lu, Shengen Yan, Yu-Wing Tai. [doi]
- Instruction-Level Data Isolation for the Kernel on ARMYeongpil Cho, Donghyun Kwon, Yunheung Paek. [doi]
- On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and ActivityJohann Knechtel, Ozgur Sinanoglu. [doi]
- DIMP: A Low-Cost Diversity Metric Based on Circuit Path AnalysisSergi Alcaide, Carles Hernández, Antoni Roca, Jaume Abella. [doi]
- Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-LearningMohamad Alawieh, Fa Wang, Xin Li. [doi]
- Crossroads: Time-Sensitive Autonomous Intersection Management TechniqueEdward Andert, Mohammad Khayatian, Aviral Shrivastava. [doi]
- Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect ArchitectureQinghang Zhao, Yongpan Liu, Wenyu Sun, Jiaqing Zhao, Hailong Yao, Xiaojun Guo, Huazhong Yang. [doi]
- Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow TrackingAndrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne. [doi]
- Extensibility-Driven Automotive In-Vehicle Architecture Design: InvitedQi Zhu, Hengyi Liang, Licong Zhang, Debayan Roy, Wenchao Li, Samarjit Chakraborty. [doi]
- Statistical Error Analysis for Low Power Approximate AddersMuhammad Kamran Ayub, Osman Hasan, Muhammad Shafique. [doi]
- Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-SchedulingMengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann. [doi]
- Safety Guard: Runtime Enforcement for Safety-Critical Cyber-Physical Systems: InvitedMeng Wu, Haibo Zeng, Chao Wang, Huafeng Yu. [doi]
- Fogging Effect Aware Placement in Electron Beam LithographyYu-Chen Huang, Yao-Wen Chang. [doi]
- A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless ApplicationsSebastian Haas, Tobias Seifert, Benedikt Nöthen, Stefan Scholze, Sebastian Höppner, Andreas Dixius, Esther Pérez Adeva, Thomas R. Augustin, Friedrich Pauls, Sadia Moriam, Mattis Hasler, Erik Fischer, Yong Chen, Emil Matús, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Love Cederström, Dennis Walter, Stephan Henker, Stefan Hänzsche, Johannes Uhlig, Holger Eisenreich, Stefan Weithoffer, Norbert Wehn, René Schüffny, Christian Mayr, Gerhard Fettweis. [doi]
- Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoRYing Wang, Huawei Li, Xiaowei Li. [doi]
- Analyzing Hardware Based Malware DetectorsNisarg Patel, Avesta Sasan, Houman Homayoun. [doi]
- Path-Specific Functional Timing Verification under Floating and Transition Modes of OperationChun-Ning Lai, Jie-Hong R. Jiang. [doi]
- Pin Accessibility-Driven Cell Layout Redesign and Placement OptimizationJaewoo Seo, Jinwook Jung, Sangmin Kim, Youngsoo Shin. [doi]
- Toggle MUX: How X-Optimism Can Lead to Malicious HardwareChristian Krieg, Clifford Wolf, Axel Jantsch, Tanja Zseby. [doi]
- Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: InvitedVladimir Dubikhin, Chris J. Myers, Danil Sokolov, Ioannis Syranidis, Alexandre Yakovlev. [doi]
- Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance ImprovementYajuan Du, Qiao Li, Liang Shi, Deqing Zou, Hai Jin, Chun Jason Xue. [doi]
- Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain LengthJuexiao Su, Lei He. [doi]
- A Clock Tree Optimization Framework with Predictable Timing QualityRickard Ewetz. [doi]
- Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair MeasurementsChen Zhou, Keshab K. Parhi, Chris H. Kim. [doi]
- FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAsShuo Wang, Yun Liang, Wei Zhang. [doi]
- Error Propagation Aware Timing Relaxation For Approximate Near Threshold ComputingAnteneh Gebregiorgis, Saman Kiamehr, Mehdi Baradaran Tahoori. [doi]
- Detailed Placement for Two-Dimensional Directed Self-Assembly TechnologyZhi-Wen Lin, Yao-Wen Chang. [doi]
- Ultra-Efficient Processing In-Memory for Data Intensive ApplicationsMohsen Imani, Saransh Gupta, Tajana Rosing. [doi]
- iClaire: A Fast and General Layout Pattern Classification AlgorithmWei-Chun Chang, Iris Hui-Ru Jiang, Yen-Ting Yu, Wei-Fang Liu. [doi]
- Formal Techniques for Effective Co-verification of Hardware/Software Co-designsRajdeep Mukherjee, Mitra Purandare, Raphael Polig, Daniel Kroening. [doi]
- Layout Hotspot Detection with Feature Tensor Generation and Deep Biased LearningHaoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young. [doi]
- Cryptography for Next Generation TLS: Implementing the RFC 7748 Elliptic Curve448 Cryptosystem in HardwarePascal Sasdrich, Tim Güneysu. [doi]
- Extensibility in Automotive Security: Current Practice and Challenges: InvitedSandip Ray, Wen Chen, Jayanta Bhadra, Mohammad Abdullah Al Faruque. [doi]
- CFPU: Configurable Floating Point Multiplier for Energy-Efficient ComputingMohsen Imani, Daniel Peroni, Tajana Rosing. [doi]
- Design of an Energy-Efficient Accelerator for Training of Convolutional Neural Networks using Frequency-Domain ComputationJong Hwan Ko, Burhan Ahmad Mudassar, Taesik Na, Saibal Mukhopadhyay. [doi]
- Energy-Efficient Execution for Repetitive App Usages on big.LITTLE ArchitecturesXianfeng Li, Guikang Chen, Wen Wen. [doi]
- Efficient Bayesian Yield Optimization Approach for Analog and SRAM CircuitsMengshuo Wang, Fan Yang, Changhao Yan, Xuan Zeng, Xiangdong Hu. [doi]
- Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space ExplorationWei Zuo, Louis-Noël Pouchet, Andrey Ayupov, Taemin Kim, Chung-Wei Lin, Shinichi Shiraishi, Deming Chen. [doi]
- Convergence-Boosted Graph Partitioning using Maximum Spanning Trees for Iterative Solution of Large Linear CircuitsYa Wang, Wenrui Zhang, Peng Li, Jian Gong. [doi]
- Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulationIoannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David Chinnery. [doi]
- Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC SimulationTim Schmidt, Guantao Liu, Rainer Dömer. [doi]
- Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and BeyondJian Kuang 0001, Evangeline F. Y. Young. [doi]
- VirtualGC: Enabling Erase-free Garbage Collection to Upgrade the Performance of Rewritable SLC NAND Flash MemoryTseng-Yi Chen, Yuan-Hao Chang, Yuan-Hung Kuan, Yu-Ming Chang. [doi]
- Modeling the Effects of AUTOSAR Overheads on Application Timing and SchedulabilityManish Chauhan, Rodolfo Pellizzoni, Krzysztof Czarnecki. [doi]
- Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural NetworksHokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda. [doi]
- LO-FAT: Low-Overhead Control Flow ATtestation in HardwareGhada Dessouky, Shaza Zeitouni, Thomas Nyman, Andrew Paverd, Lucas Davi, Patrick Koeberl, N. Asokan, Ahmad-Reza Sadeghi. [doi]
- XFC: A Framework for eXploitable Fault Characterization in Block CiphersPunit Khanna, Chester Rebeiro, Aritra Hazra. [doi]
- LiveSynth: Towards an Interactive Synthesis FlowRafael Trapani Possignolo, Jose Renau. [doi]
- Toward Optimal Legalization for Mixed-Cell-Height Circuit DesignsJianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang. [doi]
- A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis MethodologyBiying Xu, Shaolan Li, Nan Sun, David Z. Pan. [doi]
- Leveraging Compiler Optimizations to Reduce Runtime Fault Recovery OverheadFateme S. Hosseini, Pouya Fotouhi, Chengmo Yang, Guang R. Gao. [doi]
- A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: InvitedAviral Shrivastava, Mohammadreza Mehrabian, Mohammad Khayatian, Patricia Derler, Hugo A. Andrade, Kevin Stanton, Ya-Shian Li-Baboud, Edward Griffor, Marc Weiss, John C. Eidson. [doi]
- PriSearch: Efficient Search on Private DataM. Sadegh Riazi, Ebrahim M. Songhori, Farinaz Koushanfar. [doi]
- Toss-up Wear Leveling: Protecting Phase-Change Memories from Inconsistent Write PatternsXian Zhang, Guangyu Sun. [doi]
- An Architecture for Learning Stream Distributions with Application to RNG TestingAlric Althoff, Ryan Kastner. [doi]
- QuAd: Design and Analysis of Quality-Area Optimal Low-Latency Approximate AddersMuhammad Abdullah Hanif, Rehan Hafiz, Osman Hasan, Muhammad Shafique. [doi]
- Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage RegulatorsAn Zou, Jingwen Leng, Yazhou Zu, Tao Tong, Vijay Janapa Reddi, David M. Brooks, Gu-Yeon Wei, Xuan Zhang. [doi]
- Incorporating the Role of Stress on Electromigration in Power Grids with Via ArraysVivek Mishra, Palkesh Jain, Sravan K. Marella, Sachin S. Sapatnekar. [doi]
- Rescuing Memristor-based Neuromorphic Design with High DefectsChenchen Liu, Miao Hu, John Paul Strachan, Hai (Helen) Li. [doi]
- EDiFy: An Execution time Distribution FinderBoudewijn Braams, Sebastian Altmeyer, Andy D. Pimentel. [doi]
- FFD: A Framework for Fake Flash DetectionZimu Guo, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte. [doi]
- On Characterizing Near-Threshold SRAM Failures in FinFET TechnologyShrikanth Ganapathy, John Kalamatianos, Keith Kasprak, Steven Raasch. [doi]
- Minimizing Cluster Number with Clip Shifting in Hotspot Pattern ClassificationKuan-Jung Chen, Yu-Kai Chuang, Bo-Yi Yu, Shao-Yun Fang. [doi]
- Exploiting Parallelism for Convolutional Connections in Processing-In-Memory ArchitectureYi Wang, Mingxu Zhang, Jing Yang. [doi]
- Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing SystemsLixue Xia, Mengyun Liu, Xuefei Ning, Krishnendu Chakrabarty, Yu Wang. [doi]
- Accelerating Graph Community Detection with Approximate Updates via an Energy-Efficient NoCKarthi Duraisamy, Hao Lu, Partha Pratim Pande, Aananth Kalyanaraman. [doi]
- Age-aware Logic and Memory Co-Placement for RRAM-FPGAsYuan Xue, Chengmo Yang, Jingtong Hu. [doi]
- Pauli Frames for Quantum Computer ArchitecturesL. Riesebos, X. Fu, S. Varsamopoulos, Carmen G. Almudéver, Koen Bertels. [doi]
- SABER: Selection of Approximate Bits for the Design of Error Tolerant CircuitsDeepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar. [doi]
- Hardware ODE Solvers using Stochastic CircuitsSiting Liu, Jie Han. [doi]
- A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL ModelShuo Wang, Yun Liang. [doi]
- No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world BinariesWenjian He, Sanjeev Das, Wei Zhang, Yang Liu. [doi]
- An Efficient Memristor-based Distance Accelerator for Time Series Data Mining on Data CentersXiaowei Xu, Dewen Zeng, Wenyao Xu, Yiyu Shi, Yu Hu. [doi]
- Template Aware Coverage: Taking Coverage Analysis to the Next LevelRaviv Gal, Einat Kermany, Bilal Saleh, Avi Ziv, Michael L. Behm, Bryan G. Hickerson. [doi]
- ObfusCADe: Obfuscating Additive Manufacturing CAD Models Against Counterfeiting: InvitedNikhil Gupta, Fei Chen, Nektarios Georgios Tsoutsos, Michail Maniatakos. [doi]
- ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile MemoriesJoydeep Rakshit, Kartik Mohanram. [doi]
- Low-overhead Aging-aware Resource Management on Embedded GPUsHaeseung Lee, Muhammad Shafique, Mohammad Abdullah Al Faruque. [doi]
- Phase-driven Learning-based Dynamic Reliability Management For Multi-core ProcessorsZhiyuan Yang, Caleb Serafy, Tiantao Lu, Ankur Srivastava. [doi]
- A New Paradigm for Synthesis of Linear DecompressorsEmil Gizdarski, Peter Wohl, John A. Waicukauski. [doi]
- HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUsKenneth O'Neal, Philip Brisk, Emily Shriver, Michael Kishinevsky. [doi]
- Energy-Aware Standby-Sparing on Heterogeneous Multicore SystemsAbhishek Roy, Hakan Aydin, Dakai Zhu. [doi]
- Retiming of Two-Phase Latch-Based Resilient CircuitsHsiao-Lun Wang, Minghe Zhang, Peter A. Beerel. [doi]
- A Systems Approach to Computing in Beyond CMOS Fabrics: InvitedAmeya Patil, Naresh Shanbhag, Lav Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young. [doi]
- Specification, Verification and Design of Evolving Automotive Software: InvitedS. Ramesh, Birgit Vogel-Heuser, Wanli Chang, Debayan Roy, Licong Zhang, Samarjit Chakraborty. [doi]
- MOCA: an Inter/Intra-Chip Optical Network for MemoryZhehui Wang, Zhengbin Pang, Peng Yang, Jiang Xu, Xuanqi Chen, Rafael K. V. Maeda, Zhifei Wang, Luan H. K. Duong, Haoran Li, Zhe Wang. [doi]
- INVITED Challenges and Potential for Incorporating Model-Based Design in Medical Device Development: Extended AbstractLouis Lintereur. [doi]
- An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-to-Information ExtractionAlfio Di Mauro, Francesco Conti 0001, Luca Benini. [doi]
- Enabling Write-Reduction Strategy for Journaling File Systems over Byte-addressable NVRAMTseng-Yi Chen, Yuan-Hao Chang, Shuo-Han Chen, Chih-Ching Kuo, Ming-Chang Yang, Hsin-Wen Wei, Wei Kuan Shih. [doi]
- Fast Predictive Useful Skew Methodology for Timing-Driven Placement OptimizationSeungwon Kim, SangGi Do, Seokhyeong Kang. [doi]
- Deep Reinforcement Learning for Building HVAC ControlTianshu Wei, Yanzhi Wang, Qi Zhu. [doi]
- A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence ApplicationsPeng Ouyang, Shouyi Yin, Shaojun Wei. [doi]
- TIME: A Training-in-memory Architecture for Memristor-based Deep Neural NetworksMing Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie 0001, Yu Wang, Huazhong Yang. [doi]
- Latency-Aware Packet Processing on CPU-GPU Heterogeneous SystemsArian Maghazeh, Unmesh D. Bordoloi, Usman Dastgeer, Alexandru Andrei, Petru Eles, Zebo Peng. [doi]
- ESL Design in SystemC AMS: Introducing a top-down design methodology for mixed-signal systems: InvitedMartin Barnasconi, Sumit Adhikari. [doi]
- Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and ExecutionYanan Lu, Leibo Liu, Yangdong Deng, Jian Weng, Zhaoshi Li, Chenchen Deng, Shaojun Wei. [doi]
- Optimal Circuits for Parallel Bit ReversalRen Chen, Viktor K. Prasanna. [doi]
- In Quest of the Next Information Processing Substrate: Extended Abstract: InvitedSuman Datta, Alan Seabaugh, Michael T. Niemier, Arijit Raychowdhury, Darrell Schlom, Debdeep Jena, Grace Xing, H.-S. Philip Wong, Eric Pop, Sayeef Salahuddin, Sumeet Kumar Gupta, Supratik Guha. [doi]
- Correlated Rare Failure Analysis via Asymptotic Probability EvaluationJun Tao, Handi Yu, Dian Zhou, Yangfeng Su, Xuan Zeng, Xin Li. [doi]
- Graph-Based Logic Bit Slicing for Datapath-Aware PlacementChau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang. [doi]
- A-TEAM: Automatic template-based assertion minerAlessandro Danese, Nicolò Dalla Riva, Graziano Pravadelli. [doi]
- A Discrete Model for Networked Labs-on-Chips: Linking the Physical World to Design AutomationAndreas Grimmer, Werner Haselmayr, Andreas Springer, Robert Wille. [doi]
- Dynamic Platforms for Uncertainty Management in Future Automotive E/E Architectures: InvitedPhilipp Mundhenk, Ghizlane Tibba, Licong Zhang, Felix Reimann, Debayan Roy, Samarjit Chakraborty. [doi]
- Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm NodesPeter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang. [doi]
- Adaptation of Enhanced TSV Capacitance as Membrane Property in 3D Brain-inspired Computing SystemM. Amimul Ehsan, Hongyu An, Zhen Zhou, Yang Yi 0002. [doi]
- LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical DesignsTin-Yin Lai, Tsung-Wei Huang, Martin D. F. Wong. [doi]
- ArchEx: An Extensible Framework for the Exploration of Cyber-Physical System ArchitecturesDmitrii Kirov, Pierluigi Nuzzo, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli. [doi]
- Towards Design and Automation of Hardware-Friendly NOMA Receiver with Iterative Multi-User DetectionMuhammad Adeel Pasha, Momin Uppal, Muhammad Hassan Ahmed, Muhammad Aimal Rehman, Muhammad Awais Bin Altaf. [doi]
- Low-Power On-Chip Network Providing Guaranteed Services for Snoopy Coherent and Artificial Neural Network SystemsBhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan. [doi]
- TraPL: Track Planning of Local Congestion for Global RoutingDaohang Shi, Azadeh Davoodi. [doi]
- Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAsAnshuman Verma, Huiyang Zhou, Skip Booth, Robbie King, James Coole, Andy Keep, John Marshall, Wu-chun Feng. [doi]
- Concurrent Pin Access Optimization for Unidirectional RoutingXiaoqing Xu, Yibo Lin, Vinicius S. Livramento, David Z. Pan. [doi]
- RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel AttacksMehmet Kayaalp, Khaled N. Khasawneh, Hodjat Asghari Esfeden, Jesse Elwell, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel. [doi]
- Towards Aging-Induced ApproximationsHussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, Jörg Henkel. [doi]
- Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size CharacteristicShuo-Han Chen, Yen-Ting Chen, Hsin-Wen Wei, Wei Kuan Shih. [doi]
- Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal GroupsDerong Liu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan. [doi]
- SmartSwap: High-Performance and User Experience Friendly Swapping in Mobile SystemsXiao Zhu, Duo Liu, Kan Zhong, Jinting Ren, Tao Li. [doi]