Table of Contents

• Design and operational assessment of an intra-cell hybrid L2 cacheLinbin Chen, Jie Han, Weiqiang Liu, Fabrizio Lombardi. 1-6 [doi]
• AOI-based data-centric circuits for near-memory processingSalin Junsangsri, Fabrizio Lombardi. 7-12 [doi]
• Low cost multi-error correction for 3D polyhedral memoriesMihai Lefter, Thomas Marconi, George Razvan Voicu, Sorin Dan Cotofana. 13-18 [doi]
• Epsilon-greedy strategy for online dictionary learning with realistic memristor array constraintsFuxi Cai, Wei D. Lu. 19-20 [doi]
• Fully-connected single-layer STT-MTJ-based spiking neural network under process variabilityElena Ioana Vatajelu, Lorena Anghel. 21-26 [doi]
• 3EP: Low latency, low energy program-and-verify for triple-level cell phase change memoryAli Alsuwaiyan, Kartik Mohanram. 27-32 [doi]
• Low-power multiplexer designs using three-independent-gate field effect transistorsEdouard Giacomin, Jorge Romero Gonzalez, Pierre-Emmanuel Gaillardon. 33-38 [doi]
• A novel SRAM - STT-MRAM hybrid cache implementation improving cache performanceOdilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit. 39-44 [doi]
• Proposal for novel magnetic memory device with spin momentum locking materialsXiaowan Qin, Lang Zeng, Tianqi Gao, Deming Zhang, Mingzhi Long, Youguang Zhang, Weisheng Zhao. 45-46 [doi]
• Frequency modulation of spin torque nano oscillator with voltage controlled magnetic anisotropy effectZuodong Zhang, Lang Zeng, Tianqi Gao, Deming Zhang, Xiaowan Qin, Mingzhi Long, Youguang Zhang, Haiming Yu, Weisheng Zhao. 47-48 [doi]
• Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junctionGuanda Wang, Yue Zhang, Zhizhong Zhang, Jiang Nan, Zhenyi Zheng, Yu Wang, Lang Zeng, Youguang Zhang, Weisheng Zhao. 49-54 [doi]
• Architecture, design and technology guidelines for crosspoint memoriesA. Levisse, p. Royer, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean Michel Portal. 55-60 [doi]
• Transient model with interchangeability for dual-gate ambipolar CNTFET logic designXuan Hu, Joseph S. Friedman. 61-66 [doi]
• A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challengeDwaipayan Chakraborty, Sunny Raj, Sumit Kumar Jha. 67-72 [doi]
• Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOSJiajun Shi, Mingyu Li, Csaba Andras Moritz. 73-78 [doi]
• Fine-grained 3D reconfigurable computing fabric with RRAMMingyu Li, Jiajun Shi, Sachin Bhat, Csaba Andras Moritz. 79-80 [doi]
• Hybrid neural network using binary RRAM devicesMohammed Affan Zidan, YeonJoo Jeong, Wei D. Lu. 81-82 [doi]
• A logic-in-memory design with 3-terminal magnetic tunnel junction function evaluators for convolutional neural networksSumit Dutta, Saima A. Siddiqui, Felix Buttner, Luqiao Liu, Caroline A. Ross, Marc A. Baldo. 83-88 [doi]
• Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metalKarthik Yogendra, Minsuk Koo, Kaushik Roy 0001. 89-94 [doi]
• Reconfigurable processing in memory architecture based on spin orbit torqueLiang Chang, Zhaohao Wang, Youguang Zhang, Weisheng Zhao. 95-96 [doi]
• High performance and energy-efficient in-memory computing architecture based on SOT-MRAMZhezhi He, Shaahin Angizi, Farhana Parveen, Deliang Fan. 97-102 [doi]
• Approximate vector matrix multiplication implementations for neuromorphic applications using memristive crossbarsWalt Woods, Christof Teuscher. 103-108 [doi]
• SkyNet: Memristor-based 3D IC for artificial neural networksSachin Bhat, Sourabh Kulkami, Jiajun Shi, Mingyu Li, Csaba Andras Moritz. 109-114 [doi]
• Memcapacitive reservoir computingS. J. Dat Tran, Christof Teuscher. 115-116 [doi]
• CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devicesDilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf. 117-118 [doi]
• Mixing circuit based on neural associative memories and nanoelectronic 1S1R cellsArne Heittmann, Tobias G. Noll. 119-124 [doi]
• Spatio-temporal learning with arrays of analog nanosynapsesChristopher H. Bennett, Damien Querlioz, Jacques-Olivier Klein. 125-130 [doi]
• Polymorphic spintronic logic gates for hardware security primitives - Device design and performance benchmarkingS. Rakheja, N. Kani. 131-132 [doi]
• Non-temporal logic performance of an atomic switch networkKelsey Scharnhorst, Walt Woods, Christof Teuscher, Adam Z. Stieg, James K. Gimzewski. 133-138 [doi]
• Naive Bayesian inference of handwritten digits using a memristive associative memoryMohammad M. A. Taha, Christof Teuscher. 139-140 [doi]
• Automated synthesis of compact multiplier circuits for in-memory computing using ROBDDsAmad Ul Hassen. 141-146 [doi]
• A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJSudipta Bhuin, Joseph Sweeney, Samuel Pagliarini, Ayan K. Biswas, Lawrence T. Pileggi. 147-152 [doi]
• Linear regression based multi-state logic decomposition approach for efficient hardware implementationWafi Danesh, Mostafizur Rahman. 153-154 [doi]
• Ultra high density 3D SRAM cell design in Stacked Horizontal Nanowire (SN3D) fabricNaveen Kumar Macha, Sandeep Geedipally, Mostafizur Rahman. 155-161 [doi]
• Verilog - A compact model of a ME-MTJ based XNOR/NOR gateNishtha Sharma, Andrew Marshall, Jonathan Bird. 162-167 [doi]