Odilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit. A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance. In IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017, Newport, RI, USA, July 25-26, 2017. pages 39-44, IEEE, 2017. [doi]
Abstract is missing.