Odilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit. A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance. In IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017, Newport, RI, USA, July 25-26, 2017. pages 39-44, IEEE, 2017. [doi]
@inproceedings{CoiPSTB17,
title = {A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance},
author = {Odilia Coi and Guillaume Patrigeon and Sophiane Senni and Lionel Torres and Pascal Benoit},
year = {2017},
doi = {10.1109/NANOARCH.2017.8053704},
url = {http://doi.ieeecomputersociety.org/10.1109/NANOARCH.2017.8053704},
researchr = {https://researchr.org/publication/CoiPSTB17},
cites = {0},
citedby = {0},
pages = {39-44},
booktitle = {IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017, Newport, RI, USA, July 25-26, 2017},
publisher = {IEEE},
isbn = {978-1-5090-6037-5},
}