Abstract is missing.
- A Coarse-Grain Phased Logic CPURobert B. Reese, Mitchell A. Thornton, Cherrice Traver. 2-13 [doi]
- The Lutonium: A Sub-Nanojoule Asynchronous 8051 MicrocontrollerAlain J. Martin, Mika Nyström, Karl Papadantonakis, Paul I. Pénzes, Piyush Prakash, Catherine G. Wong, Jonathan Chang, Kevin S. Ko, Benjamin Lee, Elaine Ou, James Pugh, Eino-Ville Talvala, James T. Tong, Ahmet Tura. 14-23 [doi]
- SNAP: A Sensor-Network Asynchronous ProcessorClinton Kelly IV, Virantha N. Ekanayake, Rajit Manohar. 24-35 [doi]
- Congestion and Starvation Detection in Ripple FIFOsWilliam S. Coates, Robert J. Drost. 36-45 [doi]
- Adaptive Pipeline Structures fo Speculation ControlAristides Efthymiou, Jim D. Garside. 46-55 [doi]
- Energy and Performance Models for Clocked and Asynchronous CommunicationKenneth S. Stevens. 56-67 [doi]
- Timing Measurements of Synchronization CircuitsYaron Semiat, Ran Ginosar. 68-77 [doi]
- Efficient Self-Timed Interfaces for Crossing Clock DomainsAjanta Chakraborty, Mark R. Greenstreet. 78-88 [doi]
- Fourteen Ways to Fool Your SynchronizerRan Ginosar. 89-97 [doi]
- Monotonic Circuits with Complete AcknowledgementNikolai Starodoubtsev, Sergei Bystrov, Alexandre Yakovlev. 98-108 [doi]
- On the Existence of Hazard-Free Multi-Level LogicSteven M. Nowick, Charles W. O Donnell. 109-120 [doi]
- An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous CircuitsMark B. Josephs. 121-131 [doi]
- Delay-Insensitive, Point-to-Point Interconnect Using M-of-N CodesW. J. Bainbridge, W. B. Toms, David A. Edwards, Stephen B. Furber. 132-140 [doi]
- Self-Timed Ring for Globally-Asynchronous Locally-Synchronous SystemsThomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner. 141-150 [doi]
- A High-Speed Clockless Serial Link TransceiverJohn Teifel, Rajit Manohar. 151-163 [doi]
- Low-Latency Contro Structures with SlackAlexandre V. Bystrov, Danil Sokolov, Alexandre Yakovlev. 164-173 [doi]
- Asynchronous DRAM Design and SynthesisVirantha N. Ekanayake, Rajit Manohar. 174-183 [doi]
- Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph DescriptionsHiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya. 184-195 [doi]
- A New Class of Asynchronous A/D Converters Based on Time QuantizationEmmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin. 196-205 [doi]
- An Investigation into the Security of Self-Timed CircuitsZ. C. Yu, Stephen B. Furber, Luis A. Plana. 206-215 [doi]
- Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing ApplicationYee William Li, George Patounakis, Anup Jose, Kenneth L. Shepard, Steven M. Nowick. 216-226 [doi]