Table of Contents

• Toward Design Technology in 2020: Trends, Issues, and ChallengesJustin E. Harlow III. 3-4 [doi]
• Future Challenges in VLSI DesignJosé A. B. Fortes. 5-7 [doi]
• Networks-On-Chip: The Quest for On-Chip Fault-Tolerant CommunicationRadu Marculescu. 8-12 [doi]
• Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD ToolsShamik Das, Anantha Chandrakasan, Rafael Reif. 13-18 [doi]
• Bouncing Threads: Merging a New Execution Model into a Nanotechnology MemorySarah E. Frost, Arun Rodrigues, Charles A. Giefer, Peter M. Kogge. 19-28 [doi]
• Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOSKoushik K. Das, Richard B. Brown. 29-34 [doi]
• Power Comparison of Throughput Optimized IC BussesE. Malley, A. Salinas, K. Ismail, Lawrence T. Pileggi. 35-44 [doi]
• LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino CircuitsYonghee Im, Kaushik Roy. 45-54 [doi]
• Interconnect Effort - A Unification of Repeater Insertion and Logical EffortSrividya Srinivasaraghavan, Wayne Burleson. 55-61 [doi]
• Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit DesignMakram M. Mansour, Mohammad M. Mansour, Amit Mehrotra. 62-69 [doi]
• A Fine-Grain Phased Logic CPURobert B. Reese, Mitchell A. Thornton, Cherrice Traver. 70-79 [doi]
• An Efficient Calibration Technique for Systematic Current-Mismatch of D/A ConvertersKwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang. 80-86 [doi]
• Energy Benefits of a Configurable Line Size Cache for Embedded SystemsChuanjun Zhang, Frank Vahid, Walid A. Najjar. 87-91 [doi]
• Reconfigurable Fast Memory Management System Design for Application Specific ProcessorsS. Kagan Agun, J. Morris Chang. 92-100 [doi]
• System Design Approach To Power Aware Mobile ComputersJolin M. Warren, Thomas L. Martin, Asim Smailagic, Daniel P. Siewiorek. 101-106 [doi]
• Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC)Jürgen Becker, Martin Vorbach. 107-112 [doi]
• A Framework for Security on NoC TechnologiesCatherine H. Gebotys, Robert J. Gebotys. 113-120 [doi]
• Peak Power Minimization Through Datapath SchedulingSaraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi. 121-126 [doi]
• Using Dynamic Branch Behavior for Power-Efficient Instruction FetchJie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir. 127-132 [doi]
• Energy Recovering ASIC DesignConrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou. 133-138 [doi]
• A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware MicroprocessorsYu Bai, R. Iris Bahar. 139-148 [doi]
• An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold VoltagesRobert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw. 149-154 [doi]
• Low Power Test Set Embedding Based on Phase ShiftersMaciej Bellos, Dimitri Kagaris, Dimitris Nikolos. 155-160 [doi]
• Supply Voltage Scalable System Design Using Self-Timed CircuitsW. Kuang, J. S. Yuan, Abdel Ejnioui. 161-166 [doi]
• Optimal shielding/spacing metrics for low power designRavishankar Arunachalam, Emrah Acar, Sani R. Nassif. 167-172 [doi]
• An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow GraphsAbdulkadir Utku Diril, Yuvraj Singh Dhillon, Kyu-won Choi, Abhijit Chatterjee. 173-182 [doi]
• Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect OptimizationAndrew B. Kahng, Bao Liu. 183-188 [doi]
• Crosstalk Noise Analysis in Ultra Deep Submicrometer TechnologiesMohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi. 189-192 [doi]
• Block-wise Extraction of Rent s Exponents for an Extensible ProcessorTapani Ahonen, Tero Nurmi, Jari Nurmi, Jouni Isoaho. 193-202 [doi]
• A Novel Technique for Noise-Tolerance in Dynamic CircuitsSumeer Goel, Tarek Darwish, Magdy A. Bayoumi. 203-206 [doi]
• Efficient VLSI Implementation of a VLC Decoder for Universal Variable Length CodeShang Xue, Bengt Oelmann. 207-208 [doi]
• An Area-Efficient Euclidean Algorithm Block for Reed-Solomon DecoderHanho Lee. 209-210 [doi]
• An Architectural Leakage Power Simulator for VHDL Structural DatapathsChandramouli Gopalakrishnan, Srinivas Katkoori. 211-212 [doi]
• Systolic Array Implementation of Block Based Hopfield Neural Network for Pattern AssociationMing-Jung Seow, Hau T. Ngo, Vijayan K. Asari. 213-214 [doi]
• Pre-computatio of Rotatio Bits in Unidirectional CORDIC for Trigonometric and Hyperbolic ComputationsSatish Ravichandran, Vijayan K. Asari. 215-216 [doi]
• Self-Timed Design with Dynamic Domino CircuitsJung-Lin Yang, Erik Brunvand. 217-219 [doi]
• Hardware-Only Compression to Reduce Cost and Improve Utilization of Address BusesJiangjiang Liu, Nihar R. Mahapatra, Krishnan Sundaresan. 220-221 [doi]
• Automated Dynamic Memory Data Type Implementation Exploration and OptimizationMarc Leeman, Chantal Ykman-Couvreur, David Atienza, Vincenzo De Florio, Geert Deconinck. 222-224 [doi]
• Dual Threshold Voltage Circuits in the Presence of Resistive InterconnectsPer Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson. 225-230 [doi]
• Decoder-Based Multi-Context Interconnect ArchitectureAndrea Lodi 0002, Luca Ciccarelli, Andrea Cappelli, Fabio Campi, Mario Toma. 231-233 [doi]
• Titan II : An IPComp Processor for 10Gbit/sec networksIoannis Papaefstathiou. 234-235 [doi]
• Frequency Domain Approach for CMOS Ultra-Wideband RadiosHyung-Jin Lee, Dong Sam Ha. 236-237 [doi]
• Getting High-Performance Silicon from System-Level DesignW. Rhett Davis. 238-243 [doi]
• Testable Sequential Circuit Design: Partitioning for Pseudoexhaustive TestBassam Shaer, Kailash Aurangabadkar, Nitin Agarwal. 244-245 [doi]
• Joint Minimization of Power and Area in Scan Testing by Scan Cell ReorderingShalini Ghosh, Sugato Basu, Nur A. Touba. 246-249 [doi]
• Hardw are Implementation of Data Compression Algorithms for Memory Energy OptimizationLuca Benini, Davide Bruni, Alberto Macii, Enrico Macii. 250-251 [doi]
• Dynamic Coding Technique For Low-Power Data BusM. Madhu, V. Srinivasa Murty, V. Kamakoti. 252-253 [doi]
• Fast and Precise Power Prediction for Combinational CircuitsHongping Li, John K. Antonio, Sudarshan K. Dhall. 254-259 [doi]
• High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and AddersJia Di, Jiann S. Yuan, Ronald F. DeMara. 260-261 [doi]
• Code Compression Techniques for Embedded Systems and Their EffectivenessKrishnan Sundaresan, Nihar R. Mahapatra. 262-263 [doi]
• Random Characterization of Design Automation AlgorithmsSandeep K. Kondapuram, Peter M. Maurer. 264-265 [doi]
• Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global RoutingHua Tang, Hui Zhang, Alex Doboli. 266-271 [doi]
• Equalizing Filter Design for Crosstalk CancellationJihong Ren, Mark R. Greenstreet. 272-274 [doi]
• Behavioral Simulation of Power Line Noise Coupling in Mixed-Signal Systems using SystemCJan Lundgren, Bengt Oelmann, Trond Ytterdal, Patrik Eriksson, Munir Abdalla, Mattias O Nils. 275-277 [doi]
• Enhanced Techniques for Current Balanced Logic in Mixed-Signal ICsLi Yang, J. S. Yuan. 278-279 [doi]
• Quantum Voltage Comparator for 0.07 mum CMOS Flash A/D ConvertersJincheol Yoo, Kyusun Choi, Jahan Ghaznavi. 280-282 [doi]