High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders - researchr publication

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Jia Di, Jiann S. Yuan, Ronald F. DeMara. High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. In 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA. pages 260-261, IEEE Computer Society, 2003. [doi]

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