Jia Di, Jiann S. Yuan, Ronald F. DeMara. High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. In 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA. pages 260-261, IEEE Computer Society, 2003. [doi]
@inproceedings{DiYD03,
title = {High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders},
author = {Jia Di and Jiann S. Yuan and Ronald F. DeMara},
year = {2003},
url = {http://csdl.computer.org/comp/proceedings/isvlsi/2003/1904/00/19040260abs.htm},
tags = {context-aware, design},
researchr = {https://researchr.org/publication/DiYD03},
cites = {0},
citedby = {0},
pages = {260-261},
booktitle = {2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-1904-0},
}