John P. Knight - researchr alias

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Viewing Publication 1 - 14 from 14

2005

Physical resource binding for a coarse-grain reconfigurable array using evolutionary algorithmsFred Ma, John P. Knight, Calvin Plett. tvlsi, 13(5):553-563, 2005. [doi]

2004

Physical Resource Binding for a Coarse Grain Reconfigurable ArrayFred Ma, John P. Knight, Calvin Plett. ersa 2004: 109-115

2002

Compatible cell connections for multifamily dynamic logic gatesRolando Ramírez Ortiz, John P. Knight. tvlsi, 10(3):327-340, 2002. [doi]

2001

Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithmsElie Torbey, John P. Knight. tvlsi, 9(5):599-607, 2001. [doi]

1996

Optimizing Power in ASIC Behavioral SynthesisRaul San Martin, John P. Knight. dt, 13(2):58-70, 1996. [doi]

1995

Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral LevelRaul San Martin, John P. Knight. dac 1995: 42-47 [doi]

1993

Operations research in the high-level synthesis of integrated circuitsRaul San Martin, John P. Knight. cor, 20(8):845-856, 1993. [doi]

Genetic Algorithms for the Optimization of Integrated Circuits SynthesisRaul San Martin, John P. Knight. icga 1993: 432-438

1989

Scheduling and Binding Algorithms for High-Level SynthesisPierre G. Paulin, John P. Knight. dac 1989: 1-6 [doi]

Force-directed scheduling for the behavioral synthesis of ASICsPierre G. Paulin, John P. Knight. tcad, 8(6):661-679, 1989. [doi]

Algorithms for high-level synthesisPierre G. Paulin, John P. Knight. dt, 6(6):18-31, 1989. [doi]

1987

Force-Directed Scheduling in Automatic Data Path SynthesisPierre G. Paulin, John P. Knight. dac 1987: 195-202 [doi]

1986

HAL: a multi-paradigm approach to automatic data path synthesisPierre G. Paulin, John P. Knight, Emil F. Girczyc. dac 1986: 263-270 [doi]

1985

Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware CompilationEmil F. Girczyc, Raymond J. A. Buhr, John P. Knight. tcad, 4(2):134-142, 1985. [doi]

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