Noel Menezes - researchr alias

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Viewing Publication 1 - 26 from 26

2019

Session details: KeynoteNoel Menezes. ispd 2019: [doi]

2008

A true electrical cell model for timing, noise, and power grid verificationNoel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin. dac 2008: 462-467 [doi]

2007

2006

A multi-port current source model for multiple-input switching effects in CMOS library cellsChirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout. dac 2006: 247-252 [doi]

2005

Statistical static timing analysis: how simple can we get?Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail. dac 2005: 652-657 [doi]

Variability modeling and variability-aware design in deep submicron integrated circuitsFlorentin Dartu, Anirudh Devgan, Noel Menezes. glvlsi 2005: 1 [doi]

2004

Statistical timing analysis based on a timing yield modelFarid N. Najm, Noel Menezes. dac 2004: 460-465 [doi]

Repeater scaling and its impact on CADPrashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick. tcad, 23(4):451-463, 2004. [doi]

2003

The scaling challenge: can correct-by-construction design help?Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick. ispd 2003: 51-58 [doi]

2001

Optimization and Analysis Techniques for the Deep Submicron RegimeNoel Menezes, Sachin S. Sapatnekar. vlsid 2001: 3-4

1999

Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-MatchingChung-Ping Chen, Noel Menezes. dac 1999: 502-506 [doi]

Spec-Based Repeater Insertion and Wire Sizing for On-chip InterconnectNoel Menezes, Chung-Ping Chen. vlsid 1999: 476 [doi]

1997

Clustering and Load Balancing for Buffered Clock Tree SynthesisAshih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi. iccd 1997: 217-223

A sequential quadratic programming approach to concurrent gate and wire sizingNoel Menezes, Ross Baldick, Lawrence T. Pileggi. tcad, 16(8):867-881, 1997. [doi]

Moment-sensitivity-based wire sizing for skew reduction in on-chip clock netsSatyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi. tcad, 16(2):210-215, 1997. [doi]

1996

Performance computation for precharacterized CMOS gates with RC loadsFlorentin Dartu, Noel Menezes, Lawrence T. Pileggi. tcad, 15(5):544-553, 1996. [doi]

Post-processing of clock trees via wiresizing and buffering for robust designSatyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi. tcad, 15(6):691-701, 1996. [doi]

1995

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay OptimizationNoel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi. dac 1995: 690-695 [doi]

A sequential quadratic programming approach to concurrent gate and wire sizingNoel Menezes, Ross Baldick, Lawrence T. Pileggi. iccad 1995: 144-151 [doi]

1994

1993

Reliable Non-Zero Skew Clock Trees Using Wire Width OptimizationSatyamurthy Pullela, Noel Menezes, Lawrence T. Pillage. dac 1993: 165-170 [doi]

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