Abstract is missing.
- Keynote SpeakerRaul Camposano. 3 [doi]
- Important placement considerations for modern VLSI chipsPaul Villarrubia. 6 [doi]
- Convergence of placement technology in physical synthesis: is placement really a point tool?Ravi Varadarajan. 7 [doi]
- 3D thermal-ADI: an efficient chip-level transient thermal simulatorTing-Yuan Wang, Yu-Min Lee, Charlie Chung-Ping Chen. 10-17 [doi]
- Capturing crosstalk-induced waveform for accurate static timing analysisMasanori Hashimoto, Yuji Yamada, Hidetoshi Onodera. 18-23 [doi]
- Closed form expressions for extending step delay and slew metrics to ramp inputsChandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan. 24-31 [doi]
- Explicit gate delay model for timing evaluationMuzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee. 32-38 [doi]
- Signal integrity management in an SoC physical design flowMurat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda. 39-46 [doi]
- There is life left in ASICsLeon Stok, John M. Cohn. 48-50 [doi]
- The scaling challenge: can correct-by-construction design help?Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick. 51-58 [doi]
- Timing driven force directed placement with physical net constraintsKarthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin. 60-66 [doi]
- Fine granularity clustering for large scale placement problemsBo Hu, Malgorzata Marek-Sadowska. 67-74 [doi]
- Partition-driven standard cell thermal placementGuoqiang Chen, Sachin S. Sapatnekar. 75-80 [doi]
- Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioningAndrew B. Kahng, Xu Xu. 81-86 [doi]
- Optimality, scalability and stability study of partitioning and placement algorithmsJason Cong, Michail Romesis, Min Xie. 88-94 [doi]
- Benchmarking for large-scale placement and beyondSaurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden. 95-103 [doi]
- A complete design for power methodology and flow for large ASICsRaymond X. Nijssen, Ed P. Huijbregts. 106-108 [doi]
- Layout impact of resolution enhancement techniques: impediment or opportunity?Lars Liebmann. 110-117 [doi]
- Advanced routing in changing technology landscapeHardy Kwok-Shing Leung. 118-121 [doi]
- Research directions for coevolution of rules and routersAndrew B. Kahng. 122-125 [doi]
- Constrained Modern FloorplanningYan Feng, Dinesh P. Mehta, Hannah Honghua Yang. 128-135 [doi]
- An integrated floorplanning with an efficient buffer planning algorithmYuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu. 136-142 [doi]
- Floorplanning of pipelined array modules using sequence pairsMatthew Moe, Herman Schmit. 143-150 [doi]
- Efficient Steiner tree construction based on spanning graphsHai Zhou. 152-157 [doi]
- Porosity aware buffered steiner tree constructionCharles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay. 158-165 [doi]
- Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial timeJeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen. 166-173 [doi]
- Process variation aware clock tree routingBing Lu, Jiang Hu, Gary Ellis, Haihua Su. 174-181 [doi]
- An architectural exploration of via patterned gate arraysChetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi. 184-189 [doi]
- Architecture and synthesis for multi-cycle communicationJason Cong, Yiping Fan, Xun Yang, Zhiru Zhang. 190-196 [doi]
- Synthesis and placement flow for gain-based programmable regular fabricsBo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska. 197-203 [doi]
- Fishbone: a block-level placement and routing schemeFan Mo, Robert K. Brayton. 204-209 [doi]