Karthik Rajagopal - researchr alias

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Viewing Publication 1 - 9 from 9

2012

Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm processKarthik Rajagopal. isqed 2012: 159-164 [doi]

Designing better strategies against human adversaries in network security gamesRong Yang, Fei Fang, Albert Xin Jiang, Karthik Rajagopal, Milind Tambe, Rajiv T. Maheswaran. atal 2012: 1299-1300 [doi]

2009

An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage processKarthik Rajagopal, Aatmesh, Vinod Menezes. isqed 2009: 103-106 [doi]

2005

A high performance, high voltage output buffer in a low voltage CMOS processRajat Chauhan, Karthik Rajagopal, Vinod Menezes, H. M. Roopashree, Sanish Koshy Jacob. cicc 2005: 227-230 [doi]

How accurately can we model timing in a placement engine?Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin. dac 2005: 801-806 [doi]

2003

Force directed mongrel with physical net constraintsSung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna Parasuram, Amit Chowdhary, Vladimir Tiourin, Bill Halpin. dac 2003: 214-219 [doi]

Timing driven force directed placement with physical net constraintsKarthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin. ispd 2003: 60-66 [doi]

2000

TACO: timing analysis with couplingRavishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi. dac 2000: 266-269 [doi]

1998

Determination of worst-case aggressor alignment for delay calculationPaul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi. iccad 1998: 212-219 [doi]

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