Rajat Chauhan - researchr alias

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Viewing Publication 1 - 13 from 13

2021

150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT ApplicationsVipul Singhal 0001, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod, Mahesh Mehendale, Anantha Chandrakasan. vlsid 2021: 169-174 [doi]

A 0.75-5V, 15.8 nA with 1.8 μs Delay Supply Voltage Supervisor using Adaptively Biased Comparator and Sample & Hold Technique for IoTAshutosh Chitnis, Rajat Chauhan, Divya Kaur, Qadeer Khan. cicc 2021: 1-2 [doi]

2019

Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy HarvestingSundeep Javvaji, Vipul Singhal 0001, Vinod Menezes, Rajat Chauhan, Shanthi Pavan. jssc, 54(9):2590-2600, 2019. [doi]

A K-Means-Galactic Swarm Optimization-Based Clustering Algorithm with Otsu's Entropy for Brain Tumor DetectionSatyasai Jagannath Nanda, Ishank Gulati, Rajat Chauhan, Rahul Modi, Uttam Dhaked. aai, 33(2):152-170, 2019. [doi]

2018

Engineering sequence and stimuli dependent doxorubicin release from anti-nucleolin aptamer coated gold nanoparticlesRajat Chauhan, Nicholas C. Allen, Robert S. Keynton, Paula J. Bates, Mohammed T. Malik, Martin G. O. Toole. isspit 2018: 114-117 [doi]

Gold Nanoparticles Conjugate Cancer-Targeting Aptamer and Gadolinium Chelate for MR Cancer ImagingNagwa ElBaz, Rajat Chauhan, Kurtis T. James, Danial A. Malik, Mingming Zhu, Ayman El-Baz, Robert S. Keynton, Chin K. Ng, Paula J. Bates, Tariq Malik, Martin G. OaToole. isspit 2018: 520-525 [doi]

Multi-Step Bias-Flip Rectification for Piezoelectric Energy HarvestingSundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan. esscirc 2018: 42-45 [doi]

A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled SystemsManikandan R. R., Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale. vlsid 2018: 171-176 [doi]

Single Inductor Dual Output Buck Converter for Low Power Applications and Its Stability AnalysisSowmya Sankaranarayanan, Kulkarni Chaitali Vinod, Aswanth Sreekumar, Tonse Laxminidhi, Vipul Singhal, Rajat Chauhan. vlsid 2018: 347-352 [doi]

2015

Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system powerRajat Chauhan, Prajkta Vyavahare, Siva Kothamasu. isqed 2015: 357-360 [doi]

2013

Input Referred Offset Reduction in Very High Speed Differential ReceiversRajat Chauhan, Manigandan Selvam. vlsid 2013: 115-119 [doi]

2008

A Robust Level-Shifter Design for Adaptive Voltage ScalingAnkur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, H. M. Roopashree. vlsid 2008: 383-388 [doi]

2005

A high performance, high voltage output buffer in a low voltage CMOS processRajat Chauhan, Karthik Rajagopal, Vinod Menezes, H. M. Roopashree, Sanish Koshy Jacob. cicc 2005: 227-230 [doi]

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