Table of Contents

• ISAMod: A Tool for Designing ASIPs by Comparing Different ISAsShubhankar Suman Singh, Smruti R. Sarangi. 1-6 [doi]
• A Low Latency Stochastic Square Root CircuitShyamali Mitra, Debojyoti Banerjee, Mrinal K. Naskar. 7-12 [doi]
• Novel Census Transform Hardware IPAnish Reghunath, Mihir Mody, Hetul Sanghvi, Ankur. 13-16 [doi]
• Negative Voltage Generator and Current DAC Based Regulator For Flash MemoryVivek Tyagi, Shivam Kalla, Vikas Rana. 17-22 [doi]
• Adaptive Forward Body Bias Voltage GeneratorVivek Tyagi, Vikas Rana. 23-28 [doi]
• Deterministic Digital Calibration of 1.5 bits/stage Pipelined ADCs by Direct Extraction of Calibration CoefficientsChinmaye Ramamurthy, Chetan D. Parikh, Subhajit Sen. 29-34 [doi]
• Challenges in Adoption of RF to DC Converter for Micro-Scale RF Energy Harvesting SystemsArun Mohan 0001, Saroj Mondal. 35-40 [doi]
• A Novel Low-Power Electronically Tunable Higher-Order Quadrature Oscillator using CDBAShekhar Suman Borah, Ankur Singh, Mourina Ghosh. 41-46 [doi]
• In-memory realization of SHA-2 using ReVAMP architectureDebjyoti Bhattacharjee, Anirban Majumder, Anupam Chattopadhyay. 47-53 [doi]
• Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-VP. S. Babu, Snehashri Sivaraman, Deepa N. Sarma, Tripti S. Warrier. 54-59 [doi]
• Ring Oscillator with Improved DesignPooja S. Shanbhag, Sujata Kotabagi, Priyanka Buduru, Pruthvi Benagi, S. Suma, Shraddha H. 60-64 [doi]
• Variability-Aware Thermal Simulation using CNNsHameedah Sultan, Smruti R. Sarangi. 65-70 [doi]
• A 3.55 dB NF Ultra-Compact Noise-Optimized LNA for 5G mm-Wave Bands in 65nm CMOSNoble Sebastian, Chavva Subbareddy, Immanuel Raja. 71-75 [doi]
• A 0.4µA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP TechnologyFeraj Husain, Belal Iqbal, Anuj Grover. 76-81 [doi]
• Instruction Controlled In-memory Sorting on Memristor CrossbarsSumanta Pyne. 82-87 [doi]
• A Multiply Accumulator for Stochastic Numbers Without Scaling ErrorsKatsuhiro Ichikawa, Shigeru Yamashita. 88-93 [doi]
• Prospects of Two-dimensional Material-based Field-Effect Transistors for Analog/RF ApplicationsArjun Kumar, Akhilesh Rawat, Brajesh Rawat. 94-98 [doi]
• Low Power Extended Range Multi-Modulus Divider Using True-Single-Phase-Clock LogicPrasad Kulkarni, Sahil Garg, Shubhi Agrawal, Maryam Shojaei Baghini. 99-104 [doi]
• DC-DC Converter for Powering Micro-system Load in Energy Harvesting Front-endsAnirban Barman, Ashis Maity. 105-110 [doi]
• HIPER: Low Power, High Performance and Area-Efficient Hardware Accelerators for Hidden Periodicity Detection using Ramanujan Filter BanksArghadip Das, Chandrachur Majumder, Debaprasad De, Arnab Raha, Mrinal Kanti Naskar. 111-116 [doi]
• Online Optimization of Energy Consumption and Makespan for Active Replication based Scheduling Approaches for Real-time SystemsNiraj Kumar 0004, Arijit Mondal. 117-122 [doi]
• A Novel Modeling-Attack Resilient Arbiter-PUF DesignMohammad Ebrahimabadi, Mohamed F. Younis, Wassila Lalouani, Naghmeh Karimi. 123-128 [doi]
• Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir ComputingSairam Sri Vatsavai, Ishan G. Thakkar. 129-134 [doi]
• High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zoneDharmaray Nedalgi, Saroja V. Siddamal. 135-138 [doi]
• Minimization of Switching Activity of Graphene Based CircuitsSubrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das. 139-144 [doi]
• Creating Fastest Self timing Reference Path for High Speed Memory DesignsKrashna Nand Mishra, Yogeshbhai Vallabhbhai Patel. 145-150 [doi]
• A 5nm Wide Voltage Range Ultra High Density SRAM Design for L2/L3 Cache ApplicationsSriharsha Enjapuri, Deepesh Gujjar, Sandipan Sinha, Ramesh Halli, Manish Trivedi. 151-156 [doi]
• Reconfigurable HW-SW Co-design Platform for Lung Cancer Detection and ClassificationAyushparth Sharma, Kusum Lata. 157-162 [doi]
• A Few Shot Learning based Approach for Hardware Trojan Detection using Deep Siamese CNNRicha Sharma, G. K. Sharma 0001, Manisha Pattanaik. 163-168 [doi]
• 150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT ApplicationsVipul Singhal 0001, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod, Mahesh Mehendale, Anantha Chandrakasan. 169-174 [doi]
• Binary neural network based real time emotion detection on an edge computing device to detect passenger anomalyB. S. Ajay, Madhav Rao. 175-180 [doi]
• An RL based Approach for Thermal-Aware Energy Optimized Task Scheduling in Multi-core ProcessorsSudipa Mandal, Krushna Gaurkar, Pallab Dasgupta, Aritra Hazra. 181-186 [doi]
• Game Theory-Based Parameter-Tuning for Path Planning of UAVsDiksha Moolchandani, Geesara Prathap, Ilya Afanasyev, Anshul Kumar, Manuel Mazzara, Smruti R. Sarangi. 187-192 [doi]
• Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address DecodersKumari Anjali, Shubham Saha, Anuj Grover. 193-198 [doi]
• Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating EffectShashank Banchhor, Nitanshu Chauhan, Aditya Doneria, Bulusu Anand. 199-203 [doi]
• PositGen-A Verification Suite for Posit ArithmeticAnnarao Kulkarni, Shashikala Pattanshetty, Aneesh Raveendran, David Selvakumar, Sandra Jean, Vivian Desalphine. 204-209 [doi]
• Hardware Accelerator for Dual Standard Deblocking FilterP. Saravanan, B. Syndia Priyadarshini, P. Vignesh Kanna, P. Vaishnavi. 210-215 [doi]
• A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS TechnologySouradip Sen, Utkarsh Upadhyaya, Krishna Reddy Kondreddy, Arun Goyal, Sandeep Goyal, Shalabh Gupta. 216-221 [doi]
• A 27S/32S DC-balanced line coding scheme for PAM-4 signalingMiryala Chandra Shekar, Sandeep Goyal, Shalabh Gupta. 222-227 [doi]
• PreSyNC: Hardware realization of the Presynaptic Region of a Biologically Extensive Neuronal CircuitryRounak Chatterjee, Souradeep Chowdhury, Soham Mondal, Arnab Raha, Janet Paluh, Amitava Mukherjee. 228-233 [doi]
• Transistor Sizing based PVT-Aware Low Power Optimization using Swarm IntelligencePrasenjit Saha, Hema Sai Kalluru, Zia Abbas. 234-239 [doi]
• Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysisRemya Ramakrishnan, Aditya K. V. Dev, Darshik A. S, Renuka Chinchwadkar, Madhura Purnaprajna. 240-245 [doi]
• Optical Waveguide Channel Routing with Reduced Bend-Loss for Photonic Integrated CircuitsSumit Sharma 0002, Sudip Roy 0001. 246-251 [doi]
• A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band ApplicationsSanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini. 252-257 [doi]
• Efficient Hierarchical Post-Silicon Validation and DebugPandy Kalimuthu, Kanad Basu, Benjamin Carrión Schäfer. 258-263 [doi]
• Criticality based Reduction of Security Costs in a FPGA based Cloud Computing FarmKrishnendu Guha, Amlan Chakrabarti, Krishna Paul, Biswadeep Chatterjee. 264-269 [doi]
• ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration FrameworkFarhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers. 270-275 [doi]
• An Investigation on Inherent Robustness of Posit Data RepresentationIhsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers. 276-281 [doi]
• P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic ProcessorSandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine. 282-287 [doi]
• A Fast Compact Thermal Model For Smart PhonesAniali Agrawal, Anand Singh, Ankit Gola, Hameedah Sultan, Smruti R. Sarangi. 288-293 [doi]
• A 1.8 - 6.3 GHz Quadrature Ring VCO-based Fast-settling PLL for Wireline I/O in 55nm CMOSJaved S. Gaggatur. 294-298 [doi]
• Automated Low-Cost SBST Optimization Techniques for Processor TestingVasudevan Madampu Suryasarman, Santosh Biswas, Aryabartta Sahu. 299-304 [doi]
• A 0.6 V, 2nd order low-pass Gm-C filter using CMOS inverter-based tunable OTA with 1.114 GHz cut-off frequency in 90nm CMOS technologyNisarga Ramesh, Javed S. Gaggatur. 305-309 [doi]
• Neural Network based Indirect Estimation of Functional Parameters of Amplifier by extracting features from Wavelet TransformSupriyo Srimani, Kasturi Ghosh, Hafizur Rahaman 0001. 310-315 [doi]
• Training Neural Network for Machine Intelligence in Automatic Test Pattern GeneratorSoham Roy, Spencer K. Millican, Vishwani D. Agrawal. 316-321 [doi]
• An Automated Tool for Implementing Deep Neural Networks on FPGAMasoud Shahshahani, Mohammad Sabri, Bahareh Khabbazan, Dinesh Bhatia. 322-327 [doi]
• Design Considerations for Edge Neural Network Accelerators: An Industry PerspectiveArnab Raha, Sang-Kyun Kim, Deepak Mathaikutty, Guruguhanathan Venkataramanan, Debabrata Mohapatra, Raymond Sung, Cormac Brick, Gautham N. Chinya. 328-333 [doi]