Manikandan R. R., Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale. A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. In 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018. pages 171-176, IEEE Computer Society, 2018. [doi]
Abstract is missing.