A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Manikandan R. R., Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale. A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. In 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018. pages 171-176, IEEE Computer Society, 2018. [doi]

This author has not been identified. Look up 'Manikandan R. R.' in GoogleThis author has not been identified. Look up 'Vipul Kumar Singhal' in GoogleThis author has not been identified. Look up 'Rajat Chauhan' in GoogleThis author has not been identified. Look up 'Vinod Menezes' in GoogleThis author has not been identified. Look up 'Mahesh Mehendale' in Google

runs on WebDSL