Abstract is missing.
- A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODECRodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums. 1-6 [doi]
- Optimal RF design using smart evolutionary algorithmsPeter J. Vancorenland, Carl De Ranter, Michiel Steyaert, Georges G. E. Gielen. 7-10 [doi]
- CYCLONE: automated design and layout of RF LC-oscillatorsCarl De Ranter, B. De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen. 11-14 [doi]
- An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effectsCarlo Guardiani, Sharad Saxena, Patrick McNamara, Phillip Schumaker, Dale Coder. 15-18 [doi]
- Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuitsTao Pi, C.-J. Richard Shi. 19-22 [doi]
- To split or to conjoin: the question in image computationIn-Ho Moon, James H. Kukula, Kavita Ravi, Fabio Somenzi. 23-28 [doi]
- Symbolic guided search for CTL model checkingRoderick Bloem, Kavita Ravi, Fabio Somenzi. 29-34 [doi]
- Lazy symbolic model checkingJin Yang, Andreas Tiemeyer. 35-38 [doi]
- Distance driven finite state machine traversalAndreas Hett, Christoph Scholl, Bernd Becker. 39-42 [doi]
- Automatic test pattern generation for functional RTL circuits using assignment decision diagramsIndradeep Ghosh, Masahiro Fujita. 43-48 [doi]
- Interconnect testing in cluster-based FPGA architecturesIan G. Harris, Russell Tessier. 49-54 [doi]
- Improved fault diagnosis in scan-based BIST via superpositionIsmet Bayraktaroglu, Alex Orailoglu. 55-58 [doi]
- On diagnosis of pattern-dependent delay faultsIrith Pomeranz, Sudhakar M. Reddy. 59-62 [doi]
- On-chip inductance modeling and analysisKaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw. 63-68 [doi]
- A practical approach to parasitic extraction for design of multimillion-transistor integrated circuitsEileen You, Lakshminarasimh Varadadesikan, John MacDonald, Wieze Xie. 69-74 [doi]
- A rank-one update method for efficient processing of interconnect parasitics in timing analysisH. Levy, W. Scott, Don MacMillen, Jacob White. 75-78 [doi]
- On switch factor based analysis of coupled ::::RC:::: interconnectsAndrew B. Kahng, Sudhakar Muddu, Egino Sarto. 79-84 [doi]
- Life at the end of CMOS scaling (and beyond) (panel session) (abstract only)Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow. 85 [doi]
- Area and search space control for technology mappingDirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten. 86-91 [doi]
- BDS: a BDD-based logic optimization systemCongguang Yang, Maciej J. Ciesielski, Vigyan Singhal. 92-97 [doi]
- A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesisJunhyung Um, Taewhan Kim, C. L. Liu. 98-103 [doi]
- Optimal low power X OR gate decompositionHai Zhou, D. F. Wong. 104-107 [doi]
- Watermarking while preserving the critical pathSeapahn Meguerdichian, Miodrag Potkonjak. 108-111 [doi]
- Formal verification of superscale microprocessors with multicycle functional units, exception, and branch predictionMiroslav N. Velev, Randal E. Bryant. 112-117 [doi]
- Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniquesChung-Yang Huang, Kwang-Ting Cheng. 118-123 [doi]
- Reliable verification using symbolic simulation with scalar valuesChris Wilson, David L. Dill. 124-129 [doi]
- Automatic formal verification of DSP softwareDavid W. Currie, Alan J. Hu, Sreeranga P. Rajan. 130-135 [doi]
- System chip test: how will it impact your design?Yervant Zorian, Erik Jan Marinissen. 136-141 [doi]
- Test challenges for deep sub-micron technologiesKwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy. 142-149 [doi]
- Hierarchical analysis of power distribution networksMin Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw. 150-155 [doi]
- Fast power grid simulationSani R. Nassif, Joseph N. Kozhaya. 156-161 [doi]
- Current signature compression for IR-drop analysisRajat Chaudhry, David Blaauw, Rajendran Panda, Tim Edwards. 162-167 [doi]
- Impact of interconnect variations on the clock skew of a gigahertz microprocessorYing Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas. 168-171 [doi]
- A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performanceVikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha Chandrakasan, Rakesh Vallishayee, Sani R. Nassif. 172-175 [doi]
- Design closure (panel session): hope or hype?Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer. 176-177 [doi]
- A multi-interval Chebyshev collocation method for efficient high-accuracy RF circuit simulationBaolin Yang, Joel R. Phillips. 178-183 [doi]
- Projection frameworks for model reduction of weakly nonlinear systemsJoel R. Phillips. 184-189 [doi]
- A realizable driving point model for on-chip interconnect with inductanceChandramouli V. Kashyap, Byron Krauter. 190-195 [doi]
- Formal verification of an IBM CoreConnect processor local bus arbiter coreAmit Goel, William R. Lee. 196-200 [doi]
- Formal verification of iterative algorithms in microprocessorsMark Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger. 201-206 [doi]
- Efficient error detection, localization, and correction for FPGA-based debuggingJohn Lach, William H. Mangione-Smith, Miodrag Potkonjak. 207-212 [doi]
- Multiple Si layer ICs: motivation, performance analysis, and design implicationsShukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna Saraswat. 213-220 [doi]
- High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor systemV. E. Boros, Aleksandar D. Rakic, Sri Parameswaran. 221-226 [doi]
- A design of and design tools for a novel quantum dot based microprocessorMichael T. Niemier, Michael J. Kontz, Peter M. Kogge. 227-232 [doi]
- ClariNet: a noise analysis tool for deep submicron designRafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov. 233-238 [doi]
- Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technologyKenneth L. Shepard, Dae-Jin Kim. 239-242 [doi]
- Dynamic noise analysis in precharge-evaluate circuitsDinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De. 243 [doi]
- Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sourcesJanet Meiling Wang, Tuyen V. Nguyen. 247-252 [doi]
- EDA meets.COM (panel session): how E-services will change the EDA business modelJennifer Smith, Tom Quan, Andrew B. Kahng. 253 [doi]
- Symbolic timing simulation using cluster schedulingClayton B. McDonald, Randal E. Bryant. 254-259 [doi]
- Critical path analysis using a dynamically bounded delay modelSoha Hassoun. 260-265 [doi]
- TACO: timing analysis with couplingRavishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi. 266-269 [doi]
- Removing user specified false paths from timing graphsDavid Blaauw, Rajendran Panda, Abhijit Das. 270-273 [doi]
- Performance driven multi-level and multiway partitioning with retimingJason Cong, Sung Kyu Lim, Chang Wu. 274-279 [doi]
- Domino logic synthesis minimizing crosstalkKi-Wook Kim, Unni Narayanan, Sung-Mo Kang. 280-285 [doi]
- Fast post-placement rewiring using easily detectable functional symmetriesChih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska. 286-289 [doi]
- Depth optimal incremental mapping for field programmable gate arraysJason Cong, Hui Huang. 290-293 [doi]
- Code compression for low power embedded system designHaris Lekatsas, Jörg Henkel, Wayne Wolf. 294-299 [doi]
- Synthesis of application-specific memories for power optimization in embedded systemsLuca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 300-303 [doi]
- Influence of compiler optimizations on system powerMahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye. 304-307 [doi]
- Power minimization derived from architectural-usage of VLIW processorsCatherine H. Gebotys, Robert J. Gebotys, S. Wiratunga. 308-311 [doi]
- Power analysis of embedded operating systemsRobert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha. 312-315 [doi]
- Memory aware compilation through accurate timing extractionPeter Grun, Nikil D. Dutt, Alexandru Nicolau. 316-321 [doi]
- Compiling Esterel into sequential codeStephen A. Edwards. 322-327 [doi]
- Interactive co-design of high throughput embedded multimediaThierry J.-F. Omnés, Thierry Franzetti, Francky Catthoor. 328-331 [doi]
- Predicting performance potential of modern DSPsNaji Ghazal, A. Richard Newton, Jan M. Rabaey. 332-335 [doi]
- Future systems-on-chip: software of hardware design? (panel session)Brain Dipert, Danesh Tavana, Barry K. Britton, Bill Harris, Bob Boderson, Chris Rowen. 336-337 [doi]
- Embedded systems design in the new millennium (panel session)A. Richard Newton, Walden C. Rhines, Sünke Mehrgardt, Henry Samueli, Tudor Brown. 338-339 [doi]
- The design and use of simplepower: a cycle-accurate energy estimation toolWu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 340-345 [doi]
- An instruction-level functionally-based energy estimation model for 32-bits microprocessorsCarlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto. 346-351 [doi]
- Dynamic power management of complex systems using generalized stochastic Petri netsQinru Qiu, Qing Wu, Massoud Pedram. 352-356 [doi]
- Performance analysis and optimization of latency insensitive systemsLuca P. Carloni, Alberto L. Sangiovanni-Vincentelli. 361-367 [doi]
- A fast algorithm for context-aware buffer insertionAshok Jagannathan, Sung-Woo Hur, John Lillis. 368-373 [doi]
- Maze routing with buffer insertion and wiresizingMinghorng Lai, D. F. Wong. 374-378 [doi]
- Routing tree construction under fixed buffer locationsJason Cong, Xin Yuan. 379-384 [doi]
- A current driven routing and verification methodology for analog applicationsThorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke. 385-389 [doi]
- A codesign virtual machine for hierarchical, balanced hardware/software system modelingJoAnn M. Paul, Simon N. Peffers, Donald E. Thomas. 390-395 [doi]
- Operating system based software generation for systems-on-chipDirk Desmet, Diederik Verkest, Hugo De Man. 396-401 [doi]
- YAPI: application modeling for signal processing systemsErwin A. de Kock, W. J. M. Smits, Pieter van der Wolf, Jean-Yves Brunel, W. M. Kruijtzer, Paul Lieverse, Kees A. Vissers, Gerben Essink. 402-405 [doi]
- COSY communication IP sJean-Yves Brunel, W. M. Kruijtzer, H. J. H. N. Kenter, Frédéric Pétrot, L. Pasquier, Erwin A. de Kock, W. J. M. Smits. 406-409 [doi]
- Synthesis and optimization of coordination controllers for distributed embedded systemsPai H. Chou, Gaetano Borriello. 410-415 [doi]
- Application-specific memory management for embedded systems using software-controlled cachesDerek Chiou, Prabhat Jain, Larry Rudolph, Srinivas Devadas. 416-419 [doi]
- Designing systems-on-chip using coresReinaldo A. Bergamaschi, William R. Lee. 420-425 [doi]
- Verification of configurable processor coresMarinés Puig-Medina, Gülbin Ezer, Pavlos Konas. 426-431 [doi]
- Design of system-on-a-chip test access architectures under place-and-route and power constraintsKrishnendu Chakrabarty. 432-437 [doi]
- The future of system design languages (panel session)Richard Goering, Clifford E. Cummings, Steven E. Schulz, Simon Davidman, John Sanguinetti, Joachim Kunkel, Oz Levia. 438-439 [doi]
- A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceiversGerd Vandersteen, Piet Wambacq, Yves Rolain, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens. 440-445 [doi]
- High-level simulation of substrate noise generation including power supply noise couplingMarc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens. 446-451 [doi]
- Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converterGeert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen. 452-457 [doi]
- B*-Trees: a new representation for non-slicing floorplansYun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu. 458-463 [doi]
- Block placement with symmetry constraints based on the O-tree non-slicing representationYingxin Pang, Florin Balasa, Koen Lampaert, Chung-Kuan Cheng. 464-467 [doi]
- Floorplan sizing by linear programming approximationPinghong Chen, Ernest S. Kuh. 468-471 [doi]
- Timing-driven placement based on partitioning with dynamic cut-net controlShih-Lian T. Ou, Massoud Pedram. 472-476 [doi]
- Can recursive bisection alone produce routable placements?Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov. 477-482 [doi]
- Task scheduling with RT constraintsMarco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin. 483-488 [doi]
- Task generation and compile-time scheduling for mixed data-control embedded softwareJordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli. 489-494 [doi]
- Schedulability-driven performance analysis of multiple mode embedded real-time systemsYoungsoo Shin, Daehong Kim, Kiyoung Choi. 495-500 [doi]
- System design of ::::active basestations:::: based on dynamically reconfigurable hardwareAthanassios Boulis, Mani B. Srivastava. 501-506 [doi]
- Hardware-software co-design of embedded reconfigurable architecturesYanbing Li, Tim Callahan, Ervan Darnell, Randolph E. Harr, Uday Kurkure, Jon Stockwood. 507-512 [doi]
- Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chipsKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey. 513-518 [doi]
- Embedded systems education (panel abstract)Sharad Malik, D. K. Arvind, Edward A. Lee, Phil Koopman, Alberto L. Sangiovanni-Vincentelli, Wayne Wolf. 519 [doi]
- Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networksQingjian Yu, Janet Meiling Wang, Ernest S. Kuh. 520-525 [doi]
- Passive model order reduction of multiport distributed interconnectsEmad Gad, Anestis Dounavis, Michel S. Nakhla, Ramachandra Achar. 526-531 [doi]
- Predicting coupled noise in RC circuits by matching 1, 2, and 3 momentsBernard N. Sheehan. 532-535 [doi]
- Singularity-treated quadrature-evaluated method of moments solver for 3-D capacitance extractionJinsong Zhao. 536-539 [doi]
- Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applicationsZhong Wang, Michael Kirkpatrick, Edwin Hsing-Mean Sha. 540-545 [doi]
- On lower bounds for scheduling problems in high-level synthesisM. Narasimhan, J. Ramanujam. 546-551 [doi]
- Efficient building block based RTL code generation from synchronous data flow graphsJens Horstmannshoff, Heinrich Meyr. 552-555 [doi]
- System-level data format exploration for dynamically allocated data structuresPeeter Ellervee, Miguel Miranda, Francky Catthoor, Ahmed Hemani. 556-559 [doi]
- MOSFET modeling and circuit design: re-establishing a lost connection (tutorial)Daniel Foty, David W. Binkley. 560 [doi]
- Using general-purpose programming languages for FPGA designBrad L. Hutchings, Brent E. Nelson. 561-566 [doi]
- An architecture-driven metric for simultaneous placement and global routing for FPGAsYao-Wen Chang, Yu-Tsang Chang. 567-572 [doi]
- MorphoSys: case study of a reconfigurable computing system targeting multimedia applicationsHartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh. 573-578 [doi]
- Survival strategies for mixed-signal systems-on-chip (panel session)Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy. 579-580 [doi]
- Forensic engineering techniques for VLSI CAD toolsDarko Kirovski, David T. Liu, Jennifer L. Wong, Miodrag Potkonjak. 581-586 [doi]
- Fingerprinting intellectual property using constraint-additionGang Qu, Miodrag Potkonjak. 587-592 [doi]
- A Web-CAD methodology for IP-core analysis and simulationAlessandro Fin, Franco Fummi. 597-600 [doi]
- Optimizing sequential verification by retiming transformationsGianpiero Cabodi, Stefano Quer, Fabio Somenzi. 601-606 [doi]
- Efficient methods for embedded system design space explorationHarry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. 607-612 [doi]
- Synthesis-for-testability of controller-datapath pairs that use gated clocksMehrdad Nourani, Joan Carletta, Christos A. Papachristou. 613-618 [doi]
- Self-test methodology for at-speed test of crosstalk in chip interconnectsXiaoliang Bai, Sujit Dey, Janusz Rajski. 619-624 [doi]
- Embedded hardware and software self-testing methodologies for processor coresLi Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng. 625-630 [doi]
- Modeling and simulation of real defects using fuzzy logicAmir Attarha, Mehrdad Nourani, Caro Lucas. 631-636 [doi]
- Closing the gap between ASIC and custom: an ASIC perspectiveDavid G. Chinnery, Kurt Keutzer. 637-642 [doi]
- The role of custom design in ASIC ChipsWilliam J. Dally, Andrew Chang. 643-647 [doi]
- Case studies: Chip design on the bleeding edge (panel session abstract)John M. Cohn, Rob A. Rutenbar, Steve Young, Chris Malachowsky, Luis Aldaz. 648 [doi]
- Convex delay models for transistor sizingMahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar. 655-660 [doi]
- Macro-driven circuit design methodology for high-performance datapathsMahadevamurty Nemani, Vivek Tiwari. 661-666 [doi]
- Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturabilityRuiqi Tian, D. F. Wong, Robert Boone. 667-670 [doi]
- Practical iterated fill synthesis for CMP uniformityYu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky. 671-674 [doi]
- Boolean satisfiability in electronic design automationJoão P. Marques Silva, Karem A. Sakallah. 675-680 [doi]
- Analysis of composition complexity and how to obtain smaller canonical graphsJawahar Jain, K. Mohanram, Dinos Moundanos, Ingo Wegener, Yuan Lu. 681-686 [doi]
- Efficient variable ordering using aBDD based samplingYuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita. 687-692 [doi]
- GTX: the MARCO GSRC technology extrapolation systemAndrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu 0004, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester. 693-698 [doi]
- A system simulation frameworkPeter van den Hamer, W. P. M. van der Linden, Peter Bingley, N. W. Schellingerhout. 699-704 [doi]
- METRICS: a system architecture for design process optimizationStephen Fenstermaker, David George, Andrew B. Kahng, Stefanus Mantik, Bart Thielges. 705-710 [doi]
- Web-based frameworks to enable CAD RD (abstract)Olivier Coudert, Igor L. Markov, Christoph Meinel, Ellen Sentovich. 711 [doi]
- "Timing closure by design, " a high frequency microprocessor design methodologyStephen D. Posluszny, N. Aoki, David Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia. 712-717 [doi]
- Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessorJen-Tien Yen, Qichao Richard Yin. 718-723 [doi]
- A methodology for formal design of hardware control with application to cache coherence protocolsCindy Eisner, Irit Shitsevalov, Russ Hoover, Wayne G. Nation, Kyle L. Nelson, Ken Valk. 724-729 [doi]
- CGaAs PowerPC FXUAlan J. Drake, Todd D. Basso, Spencer M. Gold, Keith L. Kraver, Phiroze N. Parakh, Claude R. Gauthier, P. Sean Stetson, Richard B. Brown. 730-735 [doi]
- When bad things happen to good chips (panel session)N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang. 736-737 [doi]
- Fast methods for extraction and sparsification of substrate couplingJoe Kanapka, Joel R. Phillips, Jacob White. 738-743 [doi]
- Large-scale capacitance calculationSharad Kapur, David E. Long. 744-749 [doi]
- Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reductionChing-Han Tsai, Sung-Mo Kang. 750-755 [doi]
- Unifying behavioral synthesis and physical designWilliam E. Dougherty, Donald E. Thomas. 756-761 [doi]
- Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronizationHisaaki Katagiri, Keiichi Yasumoto, Akira Kitajima, Teruo Higashino, Kenichi Taniguchi. 762-767 [doi]
- The use of carry-save representation in joint module selection and retimingZhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.. 768-773 [doi]
- Closing the gap between analog and digitalKhaled Saab, Naim Ben Hamida, Bozena Kaminska. 774-779 [doi]
- Universal fault simulation using fault tuplesKumar N. Dwarakanath, Ronald D. Blanton. 786-789 [doi]
- A novel algorithm to extract two-node bridgesSujit T. Zachariah, Sreejit Chakravarty, Carl D. Roth. 790-793 [doi]
- Power minimization using control generated clocksM. Srikanth Rao, S. K. Nandy. 794-799 [doi]
- Bus encoding for low-power high-performance memory systemsNaehyuck Chang, Kwanho Kim, Jinsung Cho. 800-805 [doi]
- Run-time voltage hopping for low-power real-time systemsSeongsoo Lee, Takayasu Sakurai. 806-809 [doi]
- Function-level power estimation methodology for microprocessorsGang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak. 810-813 [doi]
- Emerging companies - acquiring minds want to know (panel session)Dan Schweikert, Joseph B. Costello, Rajeev Madhavan, Y. C. Pati, Judy Owen, Steve Carlson, Moshe Gavrielov. 814-815 [doi]