Chang Wu - researchr alias

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Viewing Publication 1 - 60 from 60

2024

Blockchain-Based Interpretable Electric Vehicle Battery Life Prediction in IoVSiyan Liu, Chang Wu, Jiaxin Huang 0006, Ying Zhang, Ming Ye, Yuhang Huang. iotj, 11(4):7214-7227, February 2024. [doi]

NetAssistant: Dialogue Based Network Diagnosis in Data Center NetworksHaopei Wang, Anubhavnidhi Abhashkumar, Changyu Lin, Tianrong Zhang, Xiaoming Gu, Ning Ma, Chang Wu, Songlin Liu, Wei Zhou, Yongbin Dong, Weirong Jiang, Yi Wang. NSDI 2024: [doi]

VoxelMap++: Mergeable Voxel Mapping Method for Online LiDAR(-Inertial) OdometryChang Wu, Yuan You, Yifei Yuan, Xiaotong Kong, Ying Zhang, Qiyan Li 0004, Kaiyong Zhao. ral, 9(1):427-434, January 2024. [doi]

A Parking Detection Algorithm Based on Multitransitory Finite-State Machine Using Magnetic Wireless Sensor NetworkYing Zhang, Chang Wu, Siyan Liu, Zejie Lv, Xiaoman Huang, Peng Wu. iotj, 11(5):8360-8372, 2024. [doi]

2023

Global priors guided modulation network for joint super-resolution and SDRTV-to-HDRTVGang He 0002, Shaoyi Long, Li Xu 0008, Chang Wu, Wenxin Yu, Jinjia Zhou. ijon, 554:126590, October 2023. [doi]

A Model-driven Early Warning Approach for Transmission Lines Failure under Wind StormsHaoran Chen, Shibin Bai, Zhihao Tian, Gang Liu, Changgang Li, Qiulong Ni, Chang Wu. ispec2 2023: 1-5 [doi]

FPGA Technology Mapping with Adaptive Gate DecompositionLongfei Fan, Chang Wu. fpga 2023: 135-140 [doi]

Hybrid Indoor Positioning Method of BLE and Monocular VINS-Based SmartphoneXiaotong Kong, Chang Wu, Yuan You, Zejie Lv, Zhiqi Zhao. tim, 72:1-13, 2023. [doi]

Hybrid Indoor Positioning Method of BLE and PDR Based on Adaptive Feedback EKF With Low BLE Deployment DensityXiaotong Kong, Chang Wu, Yuan You, Yifei Yuan. tim, 72:1-12, 2023. [doi]

Millimeter-Wave AlGaN/GaN MIS-HEMTs with Multiple T-Gate TechnologyJielong Liu, Chang Wu, Tao Guo, Kai Wang, Chengcheng Li, An Liu, Rui Zhou, Zhen Huang, Jiayan Wu, Minhan Mi, Xiaohua Ma. icta3 2023: 1-2 [doi]

A General-Purpose Compiler Design for Instruction-Based AI Accelerator ImplementationMengxuan Wang, Yuan Linghu, Chang Wu. asicon 2023: 1-4 [doi]

An Efficient Scheduling Algorithm for Stream ComputingKexin Wang, Jundong Xie, Yiwei Wang, Chang Wu. asicon 2023: 1-4 [doi]

AQM-based Buffer Delay Guarantee for Congestion Control in 5G NetworksChang Wu, Hancheng Lu, Yuang Chen, Chenwu Zhang, Feihong Chen. wcnc 2023: 1-6 [doi]

MPCNet: Compressed multi-view video restoration via motion-parallax complementation networkChang Wu, Gang He 0002, Xinquan Lai, Yunsong Li. NN, 167:601-614, October 2023. [doi]

HierSyn: Fast Synthesis for Large Hierarchical DesignsYishan Zhang, Zhiyong Zhang, Chang Wu. asicon 2023: 1-4 [doi]

Dual-Band Power Divider With Wide Passbands and Wide Harmonic Suppression Utilizing Multi-Mode T-Stub Loaded Slotline ResonatorsZhe Zhang, Xiaojun Bi 0003, Qiang Ma 0009, Andy Shen, Chang Wu, Tao Guo, Qinfen Xu. tcasII, 70(4):1420-1424, April 2023. [doi]

A Deep Learning Parking Detection Algorithm Using W-Shape Magnetic Wireless Sensor NetworksYing Zhang, Chang Wu, Peng Wu, Yuan You, Yifei Yuan. tim, 72:1-13, 2023. [doi]

2022

Hybrid video coding scheme based on VVC and spatio-temporal attention convolution neural networkGang He 0001, Kepeng Xu, Chang Wu, Zijia Ma, Xing Wen, Ming Sun. cvpr 2022: 1790-1793 [doi]

SDRTV-to-HDRTV via Hierarchical Dynamic Context Feature MappingGang He 0002, Kepeng Xu, Li Xu 0008, Chang Wu, Ming Sun, Xing Wen, Yu-Wing Tai. mm 2022: 2890-2898 [doi]

Towards coding for VoD application: An enhanced video compression system with a content-fitted recursive restoration networkLi Xu 0008, Chang Wu, Linyi Huang, Shengyu Wei, Gang He 0002, Yunsong Li, Xinquan Lai. dsp, 122:103368, 2022. [doi]

Characterization of Single Event Upsets of Nanoscale FDSOI Circuits Based on the Simulation and Irradiation ResultsLuchang Ding, Chang Cai, Gengsheng Chen, Zehao Wu, Jing Zhang, Chang Wu, Jun Yu. iscas 2022: 2281-2285 [doi]

Real-Time Image Inpainting using PatchMatch Based Two-Generator Adversarial Networks with Optimized Edge Loss FunctionLuchang Ding, Jing Zhang, Chang Wu, Chang Cai, Gengsheng Chen. iscas 2022: 3145-3149 [doi]

Collar Data Synthesis and Its Application for Generating Virtual Collar 3D Novel View from a Single-ViewNa Guo, Pei-wei Tsai, Hongwang Xiao, Chang Wu, Wenjuan Duan. bdcloud 2022: 476-481 [doi]

Modeling and Analyzing the Multi-Information Network Propagation Dynamics on Hot EventsYuwei She, Xinyi Jiang, Chang Wu, Fulian Yin. iccpr 2022: 609-616 [doi]

An information propagation network dynamic considering multi-platform influencesFulian Yin, Yanyan Pan, Xinyi Tang, Chang Wu, Zhen Jin, Jianhong Wu. appml, 133:108231, 2022. [doi]

2021

FM-VSR: Feature Multiplexing Video Super-Resolution for Compressed VideoGang He 0002, Shan Wu, Simin Pei, Li Xu, Chang Wu, Kepeng Xu, Yunsong Li. access, 9:88060-88068, 2021. [doi]

An Efficient Video Coding System With an Adaptive Overfitted Multi-Scale Attention NetworkGang He 0002, Chang Wu, Li Xu, Lei Li, Ziyao Xu, Weiying Xie, Yunsong Li. access, 9:64022-64032, 2021. [doi]

Dependency Graph-based High-level Synthesis for Maximum Instruction ParallelismZhenghua Gu, Wenqin Wan, Jundong Xie, Chang Wu. trets, 14(4), 2021. [doi]

Highly Efficient Modulo Loop Pipeline For High Level SynthesisChang Wu, Jundong Xie, Kexin Wang. asicon 2021: 1-4 [doi]

Hybrid Indoor Positioning System for Pedestrians With Swinging Arms Based on Smartphone IMU and RSSI of BLEYuan You, Chang Wu. tim, 70:1-15, 2021. [doi]

RSNN: A Software/Hardware Co-Optimized Framework for Sparse Convolutional Neural Networks on FPGAsWeijie You, Chang Wu. access, 9:949-960, 2021. [doi]

2020

2019

2018

Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devicesXinheng Liu, Dae-Hee Kim, Chang Wu, Deming Chen. dac 2018: [doi]

2017

Layout driven FPGA packing algorithm for performance optimizationLinfeng Mo, Chang Wu, Lei He, Gengsheng Chen. ieiceee, 14(11):20170419, 2017. [doi]

Heterogeneous computing for CNNHuizi Zhang, Chang Wu, Xiao Hu. asicon 2017: 226-229 [doi]

2016

In-place LUT polarity inVersion to mitigate soft errors for FPGAsJuexiao Su, Ju-Yueh Lee, Chang Wu, Lei He. dft 2016: 81-86 [doi]

2015

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only)Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He. fpga 2015: 276 [doi]

2014

A List Simulated Annealing Algorithm for Task Scheduling on Network-on-ChipSong Chai, Yubai Li, Jian Wang, Chang Wu. jcp, 9(1):176-182, 2014. [doi]

Providing Useful Information for Passengers Based on TTF ModelYangdong Liu, Ye Tian, Bo Yuan, Chang Wu, Weishuo Qian, Wei Mao. ithings 2014: 39-44 [doi]

2011

An analytical model for Network-on-Chip with finite input bufferJian Wang, Yubai Li, Chang Wu. fcsc, 5(1):126-134, 2011. [doi]

2009

Shortest path based simulated annealing algorithm for dynamic facility layout problem under dynamic business environmentMing Dong, Chang Wu, Forest Hou. eswa, 36(8):11221-11232, 2009. [doi]

2008

A NoC Simulation and Verification Platform Based on SystemCSong Chai, Chang Wu, Yubai Li, Zhongming Yang. csse 2008: 423-426 [doi]

Lottery Router: A Customized Arbitral Priority NOC RouterChang Wu, Yubai Li, Song Chai, Zhongming Yang. csse 2008: 411-414 [doi]

2002

Global clustering-based performance-driven circuit partitioningJason Cong, Chang Wu. ispd 2002: 149-154 [doi]

2000

Performance driven multi-level and multiway partitioning with retimingJason Cong, Sung Kyu Lim, Chang Wu. dac 2000: 274-279 [doi]

1999

Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping SolutionJason Cong, Chang Wu, Yuzheng Ding. fpga 1999: 29-35 [doi]

Simultaneous Circuit Partitioning/Clustering with Retiming for Performance OptimizationJason Cong, Honching Li, Chang Wu. dac 1999: 460-465 [doi]

Optimal FPGA mapping and retiming with efficient initial state computationJason Cong, Chang Wu. tcad, 18(11):1595-1607, 1999. [doi]

1998

Optimal FPGA Mapping and Retiming with Efficient Initial State ComputationJason Cong, Chang Wu. dac 1998: 330-335 [doi]

An efficient algorithm for performance-optimal FPGA technology mapping with retimingJason Cong, Chang Wu. tcad, 17(9):738-748, 1998. [doi]

1997

FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential CircuitsJason Cong, Chang Wu. dac 1997: 644-649 [doi]

1996

An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA DesigJason Cong, Chang Wu. iccd 1996: 572-578 [doi]

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