Table of Contents

• Comprehensive Understanding of Negative Capacitance FET From the Perspective of Transient Ferroelectric ModelMasaharu Kobayashi, Chengji Jin, Toshiro Hiramoto. 1-4 [doi]
• Enhanced Recursive Residual Network for Single Image Super-ResolutionYi Zhang, Xiaoshan He, Ming-e Jing, Yibo Fan, Xiaoyang Zeng. 1-4 [doi]
• Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power ApplicationsLiang Qi, Sai-Weng Sin, Rui Paulo Martins. 1-4 [doi]
• An Optimal Designed Compensator for PSR Flyback Converters Based on Genetic AlgorithmTianyuan Tang, Ping Luo, Chengda Deng, Qiang Wang, Liao Zhang, Bo Zhang. 1-4 [doi]
• Dual-Source Energy Cooperative Harvesting Circuit with Single InductorHanze Zheng, Yinshui Xia. 1-4 [doi]
• An FPGA-based Hardware Accelerator of RANSAC Algorithm for Matching of Images Feature PointsZiwei Zhao, Fei Wang 0036, Qi Ni. 1-4 [doi]
• A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing ModuleHao Li, Hongmei Yu, Dongsheng Liu, Peng Liu, Bo Liu. 1-4 [doi]
• Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference LayersMarco Lanuzza, Raffaele De Rose, Esteban Garzón, Felice Crupi. 1-4 [doi]
• An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification PlatformJiafeng Liu, Zhiyin Lu, Xie Xie, Jian Wang 0036, Jinmei Lai. 1-4 [doi]
• Customizing CMOS/ReRAM Hybrid Hardware Architecture for Spiking CNNTianzhi Xue, Baicheng Liu, Wenhao Sun, Song Chen 0001, Yi Kang, Feng Wu. 1-4 [doi]
• Design of Crosstalk NAND Gate Circuit Based on Interconnect Coupling CapacitanceZhiwei Zhao, Yuejun Zhang, Pengjun Wang, Huihong Zhang, Zhang Weishan. 1-4 [doi]
• MMV Subspace Pursuit (M-SP) Algorithm for Joint Sparse Multiple Measurement Vectors RecoverySujuan Liu, Lili Zheng, Lei Liu, Qianjin Lin. 1-4 [doi]
• Ultra-Low-Power Intelligent Acoustic Sensing using Cochlea-Inspired Feature Extraction and DNN ClassificationMinhao Yang, Shih-Chii Liu, Mingoo Seok, Christian Enz. 1-4 [doi]
• Reconfigurable RF Power Amplifier in 5G/4G with RF-SOI CMOSYang-yang Peng, Ping Li, Yang Li. 1-4 [doi]
• Study for NOR Flash cell burn out failure improvement in the advanced node below 65nmPeng Sun, Yun Li, Yao Yao, Peng-fei Wang. 1-4 [doi]
• A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOSJinCheng Zhang, Lihe Nie, Dong Wei, Tianxiang Wu, Shunli Ma, Junyan Ren. 1-4 [doi]
• A Fast Signal Integrity Design Model of Printed Circuit Board based on Monte-Carlo TreeTingrui Zhang, Siyu Chen, Shuwu Wei, Jienan Chen. 1-4 [doi]
• High precision low power CMOS bandgap for RFIDXian Zhang, Yong Xu. 1-4 [doi]
• Rapid Growth of SiO2 on SiC with Low Ditusing High Pressure Microwave Oxygen PlasmaShengkai Wang, Jilong Hao, Nannan You, Yun Bai, Xinyu Liu. 1-4 [doi]
• A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise CouplingYu-Lun Hsieh, Tai-Cheng Lee. 1-4 [doi]
• A Coarse-to-fine Classification for Motion Blur Kernel Size Estimation with Cascaded Neural NetworksMinyuan Ye, Lei He, Gengsheng Chen. 1-4 [doi]
• Area Optimization of MPRM Circuits Using Approximate ComputingQiuhong Ying, Lun-Yao Wang, Zhufei Chu, Yinshui Xia. 1-4 [doi]
• Balance of memory footprint and runtime for high-density routing in large-scale FPGAsWei Liu, Weilin Cong, Chengyu Hu, Peng Lu, Jinmei Lai. 1-4 [doi]
• High performance optoelectronics based on CVD Mos2Qianlan Hu, Zhenfeng Zhang, Yanqing Wu. 1-3 [doi]
• Inverse RIE micro-loading in deep etching of silicon via arrayXubo Wang, Qing Wang, Jia Zhou. 1-3 [doi]
• Architecture considerations of LTE/WCDMA wideband power amplifier for efficiency improvementAbdulraqeb Abdullah Saeed Abdo, Jie Ling, Pinghua Chen. 1-4 [doi]
• Improve DRAM Leakage Issue During RAS Operational Phase Through TCAD SimulationNing Li, Wen-Yang Jiang, Blacksmith Wu, Kanyu Cao. 1-4 [doi]
• A CMOS Half-Bridge GaN Driver with 6-30V Input Voltage Range and 5.4ns Propagation DelayHaosheng Zeng, Hong Zhang, Jianping Guo. 1-4 [doi]
• A Compact Memory Structure based on 2T1R Against Single-Event Upset in RRAM ArraysYu Ma, Dingcheng Jia, Huifan Zhang, Ruoyu Wang 0014, Pingqiang Zhou. 1-4 [doi]
• A UHF Semi-Passive RFID System with Photovoltaic/Thermoelectric Energy Harvesting for Wireless Sensor NetworksPeiqing Han, Niansong Mei, Zhaofeng Zhang. 1-4 [doi]
• 20, 000-fps Visual Motion Magnification on Pixel-parallel Vision ChipJunxian He, Xichuan Zhou, Yingcheng Lin, Chonglei Sun, Cong Shi, Nanjian Wu, Gang Luo. 1-4 [doi]
• A Lightweight Slave-Module Interface Core to Implement IEEE 1149.5 MTM-Bus Based on FPGAYalong Pang, Shuai Jiang, Lu-yuan Wang, Weiwei Liu, Ji-yang Yu, Yuehua Niu. 1-4 [doi]
• A FT Trimming Circuit Based on EPROM and Pin MultiplexingYan-Ming Li, Xiao-Xiao Wang, Xiao-Li Xi, Jian Sun, Zhong Hui Chen. 1-4 [doi]
• Approximate Multiplier Using Reordered 4-2 Compressor with OR-based Error CompensationYufeng Xu, Yi Guo, Shinji Kimura. 1-4 [doi]
• A pn-Coupled Superjunction IGBT for High Switching SpeedLei Liu, Yao Yao, Meng-Qi Wen, Yue Li, David Wei Zhang. 1-4 [doi]
• A curvature corrected bandgap reference with mismatch cancelling and noise reductionDehong Lv, Heng Ma, Fuqiang Liu, Zhiliang Hong. 1-4 [doi]
• A Micro Power High Precision Sigma-Delta ADC with Adjustable Decimation RatioYongsheng Wang, Anyi Wang, Lei Li, Chengxin Zhao. 1-4 [doi]
• OpenMPL: An Open Source Layout Decomposer: Invited PaperWei Li, Yuzhe Ma, Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu 0001, David Z. Pan. 1-4 [doi]
• An Efficient Accelerator for Sparse Convolutional Neural NetworksWeijie You, Chang Wu. 1-4 [doi]
• Influences of the Source and Drain Resistance of the MOSFETs on the Single Event Upset Hardness of SRAM cellsZhongshan Zheng, Zhentao Li, Bo Li 0051, Jiajun Luo, Zhengsheng Han. 1-3 [doi]
• High Reliability GaN FET Gate Drivers for Next-generation Power Electronics TechnologyXin-ming, Zhi-Wen Zhang, Ziwei Fan, Yao Qin, Yuan-yuan Liu, Bo Zhang 0027. 1-4 [doi]
• Method for improving energy efficiency of elliptic curve cryptography algorithm on reconfigurable symmetric cipher processorZhao Tuo, Tao Chen, Wei Li, Danyang Yang. 1-4 [doi]
• An adjustable amplitude and pulse-width laser modulation driver with active feedback for QKD experimentsChenxi Zhu, Futian Liang, Bo Feng, Xinzhe Wang, Yulong Zhu, Chengzhi Peng. 1-4 [doi]
• The Digital Front End with Dual-box Digital Pre-distortion in All-digital Quadrature TransmitterYan Hu, Tao Wang, Zhiliang Hong. 1-4 [doi]
• Multi-Thread Assembling for Fast FEM Power Delivery DC Integrity AnalysisKe Yang, Shaoyi Peng, Sheldon X.-D. Tan, Hai-Bao Chen. 1-4 [doi]
• FNSim: A Device-Circuit-Algorithm Codesigned Simulator for Flash based Neural NetworkMin Zhang, Peng Huang 0004, Yizhou Zhang, Yachen Xiang, Runze Han, Lifeng Liu, Xiaoyan Liu, JinFeng Kang. 1-4 [doi]
• Analog / Mixed-Signal / RF Circuits for Complex Signal ProcessingHaruo Kobayashi 0001, Nene Kushita, Minh Tri Tran, Koji Asami, Hao San, Anna Kuwana, Akemi Hatta. 1-4 [doi]
• A Power-Area-Efficient Low-Dropout Regulator With Enhanced Buffer Impedance AttenuationZiyun He, Shaoquan Liao, Zixin Wang, Jianping Guo. 1-4 [doi]
• A Sub-1dB NF Receiver for 1.5T Magnetic Resonance ImagingChang Yu, Xiaojing Lv, Yanhui Li, Tingting Mo. 1-4 [doi]
• High-Speed ASIC Implementation of Paillier Cryptosystem with HomomorphismChun Cai, Hiromitsu Awano, Makoto Ikeda. 1-4 [doi]
• Optimization of High Reliability and Wide SOA 100 V LDMOS Transistor with Low Specific On-ResistanceAnna Kuwana, Jun-ichi Matsuda, Haruo Kobayashi 0001. 1-4 [doi]
• A 1.26-ps-FoM Output-Capacitorless LDO with Dual-Path Active-Feedback Frequency Compensation and Current-Reused Dynamic Biasing in 65-nm CMOS TechnologyHuimin Qian, Jianping Guo. 1-4 [doi]
• Design of CMOS integrated circuits for radiation hardening and its application to space electronicsYann Deval, Hervé Lapuyade, François Rivet. 1-4 [doi]
• An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural NetworkBaicheng Liu, Song Chen 0001, Yi Kang, Feng Wu. 1-4 [doi]
• A 22-40.5 GHz UWB LNA Design in 0.15um GaAsDong Wei, JinCheng Zhang, Tianxiang Wu, Shunli Ma, Junyan Ren. 1-4 [doi]
• Automatic Hardware Design Tool Based on Reusing TransformationChongzhou Fang, Zaichen Zhang, Xiaohu You, Chuan Zhang. 1-4 [doi]
• Fine Time Resolution TDC Architectures -Integral and Delta-Sigma TypesHaruo Kobayashi 0001, Kosuke Machida, Yuto Sasaki, Yusuke Osawa, Pengfei Zhang, Lei Sha, Yuki Ozawa, Anna Kuwana. 1-4 [doi]
• An FPGA Implementation of GCN with Sparse Adjacency MatrixLuchang Ding, Zhize Huang, Gengsheng Chen. 1-4 [doi]
• Minimum Output Ripple and Fixed Operating Frequency Based on Modulation Injection for COT Ripple Control ConverterMinhTri Tran, Yifei Sun, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi 0001. 1-4 [doi]
• Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfectionsJiachen Jiang, Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun. 1-4 [doi]
• Improved Model for ESD Failure Caused by Stressing No Connect PinJingrui Ma, Qi-An Xu, Blacksmith Wu, Kanyu Cao. 1-4 [doi]
• A Fast Reduction Method for Path Process Variations Without Time-Consuming TrainingWenjie Fu, Yu Zheng, Leilei Jin, Ming Ling. 1-4 [doi]
• An FPGA based Parallel Implementation for Point Cloud Neural NetworkXitao Zheng, Mingcheng Zhu, Yuan Xu, Yutong Li. 1-4 [doi]
• Non-linear function evaluation reusing matrix-vector multipliersCe Guo, Wayne Luk, Wenguang Xu. 1-4 [doi]
• Nanoscale Devices for the end of the RoadmapFrancis Balestra. 1-4 [doi]
• An assessment of RTN-induced threshold voltage jitterJianfu Zhang 0001, Azrif Manut, Rui Gao, Mehzabeen Mehedi, Zhigang Ji, Weidong Zhang 0002, John Marsland. 1-4 [doi]
• Ultra-low power consumption Spintronics DevicesZongxia Guo, Kaihua Cao, Kewen Shi, Weisheng Zhao. 1-4 [doi]
• Circuit-Level Soft Error Rate Evaluation Approach Considering Single-Event Multiple TransientXiaoyu Zhang, Bin Liang, Ruiqiang Song. 1-4 [doi]
• A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB ReceiversYuting Yao, Jipeng Wei, Manxin Li, Shunli Ma, Fan Ye 0001, Junyan Ren. 1-4 [doi]
• Self-heating Induced Variability and Reliability in Advanced Logic Devices and CircuitsXiaoyan Liu, Wangyong Chen, Linlin Cai, Gang Du, Xing Zhang. 1-4 [doi]
• A design of a wideband balanced limited low noise amplifierLi Ming, Zeng Zhi, Wei Hongtao. 1-3 [doi]
• Graphene Top-gated Mos2 PhototransistorsYaochen Sheng, Xinyu Chen, Fuyou Liao, Jianan Deng, Jing Wan, Wenzhong Bao. 1-3 [doi]
• Monolithic Co-integration of III-V Materials into Foundry Si-CMOS in a Single Chip for Novel Integrated CircuitsXing Zhou, Siau Ben Chiah, Binit Syamal, Kenneth Eng-Kian Lee. 1-4 [doi]
• A Optimized PPD CMOS Pixel with 26.09 % Transfer Efficiency Improvement and 43.34 % Crosstalk Suppression for I-ToF ApplicationJunwei Yang, Weiwei Shi 0001, Zhiyu Huang, Yuan Xu, Yanghao Zheng, Xuanbin Fang. 1-4 [doi]
• A Implementation for Built-in Self-Testing of RapidIO by JTAGChunmei Hu, Zhenyang Zhang, Yang Guo, Jingyan Xu. 1-4 [doi]
• A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock NetworkJie Li, Liyi Xiao, Hongchen Li, Lulu Liao, Chenxu Wang. 1-4 [doi]
• A High-Linear Digital-to-Phase Converter in 40nm CMOSYu Ji, Li Ding, Jing Jin. 1-4 [doi]
• Deploying and Optimizing Convolutional Neural Networks on Heterogeneous ArchitectureJunning Jiang, Liang Cai, Feng Dong, Kehua Yu, Ke Chen, Wei Qu, Jianfei Jiang. 1-4 [doi]
• A Precise Block-Based Statistical Timing Analysis with MAX Approximation Using Multivariate Adaptive Regression SplinesLeilei Jin, Wenjie Fu, Yu Zheng, Hao Yan. 1-4 [doi]
• Multi-Phase Full/Half Wave Type Resonant Converters with Automatic Current Balance against Element VariationChen-Hao Zhang, Yifei Sun, Tran Minh Tri, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi 0001. 1-4 [doi]
• Configurable Hybrid Output Driver for GPIO with Wide Supply Voltage Range of 1.05V-3.70VSiddharth Katare, Nagaveni Subramanya. 1-3 [doi]
• A Variation Aware Register Clustering Methodology in Near-Threshold RegionXiangnan Song, Shiying Zhang, Ju Zhou, Xuexiang Wang. 1-4 [doi]
• A High Reliability 500 µW Resistance-to-Digital Interface Circuit for SnO2 Gas Sensor IoT ApplicationsJianguo Yang, Xiaowen Li, Qingting Ding, Xiaoyong Xue, Xiaoxin Xu, Qing Luo, Hangbing Lv, Ming Liu 0022. 1-4 [doi]
• Ultra-Low-Power CMOS Temperature Sensor for UHF RFID SystemsKun Peng, Yang Xu, Mingqian Sun. 1-4 [doi]
• Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy ComputingJian Chen, Wenfeng Zhao, Yajun Ha. 1-4 [doi]
• An Automatic Slope-Calibrated Ramp Generator for Single-Slope ADCsShoudong Huang, Wengao Lu, Ye Zhou, Shanzhe Yu, Yacong Zhang, Xueyou Shi, Zhongjian Chen. 1-4 [doi]
• Hardware Implementation of Convolutional Neural Network for Face Feature ExtractionRu Ding, Xuemei Tian, Guoqiang Bai 0001, Guangda Su, Xingjun Wu. 1-4 [doi]
• A digitalized RRAM-based Spiking Neuron Network system with 3-bit weight and unsupervised online learning schemeDanqing Wu, Shilin Yan, Haodi Tang, Yu Wang, Jiayun Feng, Xianwu Hu, Jiaxin Cao, Yufeng Xie. 1-4 [doi]
• SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 TransistorsYuting Yao, Manxin Li, Tianxiang Wu, Hu Xu, Shunli Ma, Wenzhong Bao, Junyan Ren. 1-4 [doi]
• The Design and Performance Comparison of Wide Bandwidth LNA with Three Different Kinds of TechnologiesHuashu Wang, Wei Ma, Zhiming Xiao, Wei-Chih Cheng, Liang Wang, Fanming Zeng, Hongyu Yu, Weibo Hu. 1-4 [doi]
• A 60GHz Digitally-Controlled Differential Reflection-type Phase Shifter in 65-nm CMOS with Low Phase ErrorWentao Lv, Xiaokang Niu, Lianming Li. 1-4 [doi]
• Ultrahigh-Speed One-Chip CMOS Transceiver with 300-GHz BandMinoru Fujishima. 1-4 [doi]
• An Area-Efficient Multi-Rate Digital DecimatorQi Li, Yujun Shu, Yongzhen Chen, Jiangfeng Wu. 1-4 [doi]
• An Optimized Modeling Method for Transformer DesignYingying Liang, Xiaoming Liu 0008, Jing Jin. 1-4 [doi]
• Deep Spiking Convolutional Neural Networks for Programmable Neuro-synaptic SystemChenglong Zou, Xinan Wang, Boxing Xu, Yisong Kuang, Xiaoxin Cui. 1-4 [doi]
• Collaborative Implementation of Hardware-Oriented GBDT Compress Algorithm Based on DSP+FPGAYafei Li, Kuizhi Mei, Xiao Wang 0019, Zeng Zhang, Hejie Yu. 1-4 [doi]
• Scheduling Algorithm Based on System of Difference Constraints Using Network FlowHao Jiang, Yang Fan, Xuan Zeng 0001. 1-4 [doi]
• BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware OverheadJiexian Ge, Xiaoxin Cui, Kanglin Xiao, Chenglong Zou, Yi-Hsiang Chen, Rongshan Wei. 1-4 [doi]
• Design of High-Speed Drivers for 56Gb/s PAM4 Optical Communications in CMOSNan Qi, Nanjian Wu. 1-4 [doi]
• High throughput multi-code LDPC encoder for CCSDS standardJinfou Xie, Shixian Li, Yun Chen 0001, Qichen Zhang, Xiaoyang Zeng. 1-4 [doi]
• The Advances of OTP Memory for Embedded Applications in HKMG Generation and BeyondSteve S. Chung. 1-4 [doi]
• An Adder-Segmentation-based FIR for High Speed Signal ProcessingJinghao Ye, Masao Yanagisawa, Youhua Shi. 1-4 [doi]
• Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG SystemsChun-Ting Chen, Tsung-Yi Tsai, Yi-Jen Chiu, Chua-Chin Wang. 1-4 [doi]
• A wide range and high resolution two-step TDC for millimeter-wave band ADPLLJieyang Li, Ting Yi, Zhiliang Hong. 1-4 [doi]
• An Obfuscated Challenge Design for APUF to Resist Machine Learning AttacksBo Chen, Pengjun Wang, Gang Li. 1-4 [doi]
• An Ultra-Low Power Cycle-by-Cycle Current Limiter Suitable for Switching-Mode Power Supply with 2.2 MHz FrequencyYue Shi, Jiawen Wang, JianWen Cao, Zekun Zhou. 1-4 [doi]
• On-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks: Invited PaperMakoto Nagata. 1-4 [doi]
• Systematic Construction of Resistor Ladder Network for N-ary DACsManato Hirai, Shuhei Yamamoto, Hirotaka Arai, Anna Kuwana, Hiroshi Tanimoto, Yuji Gendai, Haruo Kobayashi 0001. 1-4 [doi]
• An FPGA based verification platform for pipeline ADC digital calibration technologyYuehong Gang, Min Luo, Mingyu Wang. 1-4 [doi]
• Defect-Tolerant and Energy-Efficient Training of Multi-Valued and Binary Memristor Crossbars for Near-Sensor Cognitive ComputingKhoa Van Pham, Tien Van Nguyen, Kyeong-Sik Min. 1-4 [doi]
• Switching of 3300V Scaled IGBT by 5V Gate DriveToshiro Hiramoto, K. Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, T. Sarava, Hiroshi Iwai, A. Ogura, Shinichi Nishizawa, Ichiro Omura, H. Ohashi, K. Itou, T. Takakura, M. Fukui, S. Suzuki, Ken Takeuchi, Masanori Tsukuda, Y. Numasawa. 1-3 [doi]
• Design of Current-Assisted Photonic Demodulator (CAPD) for Time-of-Flight CMOS Image SensorCristine Jin Estrada, Chen Xu, Mansun Chan. 1-4 [doi]
• A 96kb, 0.36V, Energy-Efficient 8T-SRAM with Column-Selection and Shared Buffer-Foot Techniques for EEG ProcessorLiang Wen, Yu Liu, Wei Mo, Jing Zhang, Shiqian Qi, Jianping Lv, Yuejun Zhang. 1-4 [doi]
• Efficient Belief Propagation List Decoding of Polar CodesYuqing Ren, Weihong Xu, Zaichen Zhang, Xiaohu You, Chuan Zhang. 1-4 [doi]
• GaN Schottky Diode Model for THz Multiplier Design with Consideration of Self-heating EffectXubo Song, Yuangang Wang, Zhihong Feng, Yuanjie Lv, Yamin Zhang, Lisen Zhang, Shixiong Liang, Xin Tan, Shaobo Dun, Dabao Yang, Zhirong Zhang. 1-3 [doi]
• A Method to Design 5-Bit Burst Error Correction Code against the Multiple Bit Upset (MBU) in MemoriesJia-Qiang Li, Li-yi Xiao, Liu He, Hao-Tian Wu. 1-4 [doi]
• Performance Investigation of Uniaxially Tensile Stressed Ge n-FinFETs Formed on Biaxially Strained GeOI Substrates And Its Impact On Ge CMOS InvertersRan Cheng, Ming Tian, Changfeng Wang, Zhimei Cai, Jie Zhang, Yan-yan Zhang, Yi Zhao. 1-4 [doi]
• An Automatically Selective Signal Combining Algorithm and System for Low SNR ECG SignalsLeiou Wang, Donghui Wang. 1-4 [doi]
• Dynamics of Ferroelectric and Ionic Memories: Physics and ApplicationsAlan C. Seabaugh, Paolo Paletti, Anwesha Palit, Karla González-Serrano, Pratyush Pandey. 1-4 [doi]
• Learning Sparse Patterns in Deep Neural NetworksWeijing Wen, Fan Yang 0001, Yangfeng Su, Dian Zhou, Xuan Zeng 0001. 1-4 [doi]
• A Low Complexity DDS Based On Optimized CORDIC AlgorithmShang Ma, Xuesi Wang, Yongjie Li, Kai Long, Bixin Zhu, Xin Lei. 1-5 [doi]
• UVM-based Functional Coverage Driven AXI4-Stream VerificationChunlin Xu, Wei Ni, Yukun Song. 1-4 [doi]
• A Simple Steady Timing Resilient Sample Based on Delay Data Sense DetectionXuemei Fan, Rujin Wang, Qin Zeng, Hao Liu, Shengli Lu. 1-4 [doi]
• RF Transceiver System Design: From Protocols to SpecificationsAng Hu, Dongsheng Liu, Zirui Jin, Cong Zhang, Ke-feng Zhang, Lan-qi Liu. 1-4 [doi]
• A Calibration Technique for Two-Step Single-Slope Analog-to-Digital ConverterWenjie Huang, Qihui Zhang, Jing Li 0022, Zhong Zhang 0002, Heng Deng, Ning Ning, Qi Yu 0002. 1-4 [doi]
• Simulation Study on Novel High Voltage Transient Voltage Suppression DiodesCong Liu, MouFu Kong, Hanzhi Chen, Bo Yi, Bingke Zhang, Xingbi Chen. 1-4 [doi]
• A High-speed Dynamic Domino Full Adder Based on DICG Positive FeedbackXiaotian Zhang, Pengjun Wang, Yunfei Yu, Yuejun Zhang, Shunxin Ye. 1-4 [doi]
• Variation Analysis of Interconnect Capacitance and Process Corner in Advanced CMOS Process with Double Patterning TechnologyZhimei Cai, Zhiyong Han, Ming Tian, Changfeng Wang, Xiaoming Hu, Ran Cheng, Yi Zhao. 1-4 [doi]
• A Web-based Waveform Viewer for BR0101 Chip Testing PlatformXinyu He, Xie Xie, Jinmei Lai, Jian Wang 0036. 1-4 [doi]
• Smart Gate Driver ICs for GaN Power TransistorsWei-Jia Zhang, Jingshu Yu, Wai Tung Ng. 1-4 [doi]
• A Readout Circuit of Microchannel Plate Light Detector in 0.13um CMOS TechnologyHaoran Gong, Yunhao Fu, Ning Ding, Jiaqi Jiang, Yuchun Chang. 1-4 [doi]
• A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech SynthesisRiyong Zheng, Chenghao Wang 0006, Jun Han 0003, Xiaoyang Zeng. 1-3 [doi]
• Power optimization for FPRM logic using approximate computing techniqueYichen Wang, Lunyao Wang. 1-4 [doi]
• Buffer Sizing for Near-Threshold Clock Tree using Improved Genetic AlgorithmYiran Sun, Ju Zhou, Shiying Zhang, Xuexiang Wang. 1-4 [doi]
• Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental FluctuationTakuya Asuke, Ryo Kishida, Jun Furuta, Kazutoshi Kobayashi. 1-4 [doi]
• Parallel Global Placement on CPU via Parallel ReductionHuaidong Gao, Fan Yang 0001, Dian Zhou, Xuan Zeng 0001. 1-4 [doi]
• A 36-40 GHz VCO with bonding inductors for millimeter wave 5G CommunicationTianxiang Wu, JinCheng Zhang, Dong Wei, Lihe Nie, Yuting Yao, Shunli Ma, Junyan Ren. 1-4 [doi]
• EMI Noise Reduction and Output Ripple Cancellation for Full-Wave Type Soft-Switching ConverterYifei Sun, Minh Tri Tran, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi 0001. 1-4 [doi]
• Analysis and Optimal Design of a New Single-Photon MemristorPeng Bo 0003, Jin Xiang-Liang. 1-4 [doi]
• Adaptive Low-Rank Tensor Approximation for SRAM Yield Analysis using Bootstrap ResamplingXiao Shi, Jinlong Yan, Hao Yan, Jiajia Zhang, Jinxin Wang, Longxing Shi, Lei He. 1-4 [doi]
• High-Bandwidth Wide-Output-Swing Linear Amplifier for LTE-100MHz Envelope TrackingMingfeng Chen, Fuqiang Liu, Heng Ma, Zhiliang Hong. 1-4 [doi]
• A GaSb/In0.4Ga0.6As Heterojunction Z-Shaped Tunnel Field-Effect Transistor with High PerformanceJiarui Bao, Shuyan Hu, Guangxi Hu, Laigui Hu, Ran Liu 0001, Lirong Zheng 0001. 1-4 [doi]
• A Low-Temperature-Coefficient and High-PSRR Bandgap Reference for Readout Circuit of SPADXuefeng Ye, Duoduo Zeng, Xiangliang Jin, Yang Wang. 1-4 [doi]
• Genetic Architecture Search for Binarized Neural NetworksYangyang Chang, Gerald E. Sobelman, Xiaofang Zhou 0002. 1-4 [doi]
• Research on the impact of different benchmark circuits on the representative path in FPGAsJiqing Xu, Zhengjie Li, Yunbing Pang, Jian Wang, Gang Qu, Jinmei Lai. 1-3 [doi]
• Design Considerations on Integrated Rectifiers with High Efficiency and Wide Input Power Range for RF Energy HarvestingMo Huang, Tingxu Hu, Xiu Yin Zhang, Yan Lu 0002. 1-4 [doi]
• Performance optimization for LDO regulator based on the differential evolutionJintao Li, Yanhan Zeng, Hailong Wu, Ruguo Li, Jun Zhang, Hong-Zhou Tan. 1-4 [doi]
• A Single-Event Upset Evaluation Approach Using Ion-Induced Sensitive AreaRuiqiang Song, Jinjin Shao, Bin Liang, Yaqing Chi, Jianjun Chen. 1-4 [doi]
• A 20GS/s Track-and-Hold Amplifier based on InP DHBT ProcessJian Gong, Zirun Zhao, Ziqing Wang, Yonghui Wu, Yong Cui. 1-4 [doi]
• A Class-F3 VCO with 104% Ultra-Wide Band Tuning Range and -125dBc/Hz Phase NoiseHaoyang Zhou, Wei Li, Tao Wang, Jiao Ye, Chuangguo Wang. 1-4 [doi]
• An Improved InP HEMT Small Signal Model with RC NetworkShixing Qiao, HongLiang Lv, YuMing Zhang, YiMen Zhang, Peng Ding. 1-4 [doi]
• Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC CodesSuwen Song, Jing Tian, Jun Lin, Zhongfeng Wang. 1-4 [doi]
• A New Approximate Multiplier Design for Digital Signal ProcessingYue Zhao, Tong Li, Feng Dong, Qin Wang, Weifeng He, Jian-Fei Jiang. 1-4 [doi]
• Design of the admittance detecting circuit for silicon waveguides using the capacitor-integration methodHong Xiang Li, Wen-hui Li, Wei-Wei Chen, Peng-Jun Wang. 1-4 [doi]
• Simulation Study of Trench IGBT with Diode-Clamped P-Well for High dI/dt and dV/dt ControllabilityRongxin Chen, Bo Yi, MouFu Kong, Xingbi Chen. 1-4 [doi]
• Design of High Dynamic Range and Digitalized Readout Integrated Circuit for LWIR FPAsJun Qiao, Xiao Wang, Yaohong Zhao. 1-3 [doi]
• A Grain-Adaptive Computing Structure for FPGA CNN AccelerationXinyuan Qu, Zhihong Huang, Ning Mao, Yu Xu, Gang Cai, Zhen Fang. 1-4 [doi]
• A New Uplink Channel Estimation Architecture for Massive MIMO Systems with PDMAZhenhao Ji, Yahui Ji, Bolei Wang, Feifei Gao, Huizheng Wang, Chuan Zhang. 1-4 [doi]
• An efficient ASIC Implementation of QARMA Lightweight AlgorithmConghui Zhao, Yingjian Yan, Wei Li. 1-4 [doi]
• A 16/32Gb/s NRZ/PAM4 Receiver with Dual-Loop CDR and Threshold Voltage CalibrationSonghao Guo, Li Ding, Jing Jin. 1-4 [doi]
• Frequency Estimation Sampling Circuit Using Analog Hilbert Filter and Residue Number SystemYudai Abe, Shogo Katayama, Congbing Li, Anna Kuwana, Haruo Kobayashi 0001. 1-4 [doi]
• Circuit Design Challenges in Computing-in-Memory for AI Edge DevicesXin Si, He Qian, Meng-Fan Chang, Cheng-Xin Xue, Jian-Wei Su, Zhixiao Zhang, Sih-Han Li, Shyh-Shyuan Sheu, Heng-Yuan Lee, Ping-Cheng Chen, Huaqiang Wu. 1-4 [doi]
• An Optimized Face Recognition for Edge ComputingYuan Xie, Luchang Ding, Aaron Zhou, Gengsheng Chen. 1-4 [doi]
• Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator ArraysYu-Cheng Su, Kang-Yu Chang, Yu-Tung Chin, Chia-Wen Chang, Shyh-Jye Jou. 1-4 [doi]
• Design of Asynchronous High Throughput SHA-256 Hardware Accelerator in 40nm CMOSJunshang Li, Zishang He, Yajie Qin. 1-4 [doi]
• A Low-delay Configurable Register for FPGAZhi-Yin Lu, Jia-Feng Liu, Yunbing Pang, Zheug-Jie Li, Yufan Zhang, Jin-mei Lai, Jian Wang. 1-4 [doi]
• Wireless Sensor Brain Machine Interfaces for Closed-loop Neuroscience StudiesXilin Liu, Milin Zhang, Han Hao, Andrew G. Richardson, Timothy H. Lucas, Jan Van der Spiegel. 1-4 [doi]
• An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic ComputingXinyue Zhang, Jiahao Song, Yuan Wang, Yawen Zhang, Zuodong Zhang, Runsheng Wang, Ru Huang. 1-4 [doi]
• Oxygen-plasma-based digital etching for GaN/AlGaN high electron mobility transistorsJingyi Wu, Hongyu Yu, Yang Jiang, Zeyu Wan, Siqi Lei, Wei-Chih Cheng, Guangnan Zhou, Robert Sokolovskij, Qing Wang, Guangrui Maggie Xia. 1-4 [doi]
• Efficient Photometric Alignment for Around View Monitor SystemCong Lai, Guangyu Wang, Qingyu Yang, Hongbin Sun 0001. 1-4 [doi]
• A Polymorphic Circuit Interoperability FrameworkTimothy Dunlap, Gang Qu, Jinmei Lai. 1-4 [doi]
• Security Analysis and Modeling Attacks on Duty Cycle Multiplexer PUFYunhao Xu, Yingjie Lao, Weiqiang Liu, Chuan Zhang. 1-4 [doi]
• Radiation Hardened Design of Pipeline and Register File in ProcessorLi-yi Xiao, Yuan-Gang Wang, Zu-Qiang Zhang, Jia-Qiang Li, Jie Li. 1-4 [doi]
• Latency Minimal Scheduling with Maximum Instruction ParallelismZhenghua Gu, Wenqin Wan, Chang Wu. 1-4 [doi]
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• Advanced Simulation of RRAM Memory CellsToufik Sadi, Oves Badami, Vihar P. Georgiev, Jie Ding, Asen Asenov. 1-4 [doi]
• Evaluation of Null Method for Operational Amplifier Short-Time TestingRiho Aoki, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Yuto Sasaki, Kosuke Machida, Takayuki Nakatani, Jianlong Wang, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi 0001. 1-4 [doi]
• Automatic Correction of Current Imbalance for Multi-Phase COT Ripple-Based Control DC-DC ConverterShogo Katayama, Jing Li, Yifei Sun, Tran Minh Tri, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi 0001. 1-4 [doi]
• Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination CircuitLinzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao. 1-4 [doi]
• Post-Si Nano Device TechnologyKazuhiko Endo. 1 [doi]
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• Realization of Nanoscale Neuromorphic Memristor Array with Low Power ConsumptionCaidie Cheng, Teng Zhang, Chang Liu, Jiadi Zhu, Liying Xu, Xiaoqin Yan, Yuchao Yang, Ru Huang. 1-4 [doi]
• A 5-bit, 87-fs Step, Constant-Slope, Charge-Sharing-Based Encoding Digital-to-Time Converter in 130nm CMOSJunyao Wang, Hairui Wang, Bo Wang. 1-4 [doi]
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• 3D Vertical RRAM Array and Device Co-design with Physics-based Spice ModelWeiiie Xu, Yudi Zhao, Peng Huang 0004, Xiaoyan Liu, JinFeng Kang. 1-4 [doi]
• Pulse Coding Control Switching Converter with Adjustable Conversion Voltage Ratio Notch Frequency Generation in Noise SpectrumYifei Sun, Minh Tri Tran, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi 0001. 1-4 [doi]
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• The Design and Implementation of High Speed Hybrid Radices Reconfigurable FFT ProcessorQiao Yuan, Huajian Zhang, Yukun Song, Chongyang Li, Xueyi Liu, Zheng Yan. 1-4 [doi]
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• ANN Based Adaptive Successive Cancellation List Decoder for Polar CodesWenqing Song, Yuxiang Fu, Qinyu Chen, Li Li 0003, Chuan Zhang. 1-4 [doi]
• A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring OscillatorXinning Liu, Song Jia, Hanzun Zhang. 1-4 [doi]
• 2 0.05-0.9GHz Low-Power Multi-phase Non-overlap Clock Generator in 40 nm CMOSZhigang Li, Xiaofei Wang, Jing Jin. 1-4 [doi]
• High Intensity Focused Ultrasound for Noninvasive Medical ApplicationsMing Zhang 0007, Nicolas Llaser. 1-4 [doi]
• CoDRAM: A Novel Near Memory Computing Framework with Computational DRAMYu Ma, Linfeng Zheng, Pingqiang Zhou. 1-4 [doi]
• An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic UnitDanyang Yang, Zibin Dai, Wei Li, Tao Chen. 1-4 [doi]
• Dual-Threshold Independent-Gate TFET with Tri-side TunnelingPengfeng Zhang, Jianping Hu. 1-4 [doi]
• Circuit Design Challenges of ADC for the Application in Multiple Physiological Parameters Detection SystemYe Yuan, Song Ma, Yuhua Cheng. 1-4 [doi]
• A Low On-state Voltage and Large Current Capability Thin SOI-LIGBT with Trench NMOSJun Huang, MouFu Kong, Xingbi Chen. 1-4 [doi]
• A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling PeriodShumin Zhang, Yuefeng Cao, Fan Ye 0001, Junyan Ren. 1-4 [doi]
• A CMOS Random Number Generator with Noise-Coupled Voltage-Controlled OscillatorsChung Fai Au-Yeung, Yiu Kei Li. 1-4 [doi]
• Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked LoopSheng Zhang, Song Jia, Hanzun Zhang, Rongshan Wei, Weixin Gai. 1-4 [doi]
• An FPGA-based log-structure Flash memory system for space explorationHuanlin Luo, Yunbo Liu, Hai Ren, Tiantian Zhang, Jian Wang, Jinmei Lai. 1-4 [doi]
• Flash-based Computing in-Memory Scheme for IOTJ. F. Kang, P. Huang, R. Z. Han, Y. C. Xiang, X. L. Cui, X. Y. Liu. 1-4 [doi]
• A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural NetworksYuan Cheng, Ngai Wong, Xiong Liu, Leibin Ni, Hai-Bao Chen, Hao Yu 0001. 1-4 [doi]
• Output Voltage Ripple Reduction with Nosie Spread Spectrum for Dual-Phase LLC Resonant ConverterShogo Katayama, Noriyuki Oiwa, Yasunori Kobori, Anna Kuwana, Harno Kobayashi. 1-4 [doi]
• Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk ProcessYuto Tsukita, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi. 1-4 [doi]
• Design and implementation of Serial ATA pbysical layer on FPGAXie Xie, Qinghua Duan, Jiafeng Liu, Jian Wang 0036, Jinmei Lai. 1-4 [doi]
• A 35µW Receiver Front-End with 35% wireless energy harvesting efficiency for Wearable Medical ApplicationsZirui Jin, Ang Hu, Zilong Liu, Dongsheng Liu. 1-4 [doi]
• An On-Time Generator with Zero Quiescent Power Consumption Suitable for AOT Buck ConvertersZekun Zhou, Zhengyang Jin, JianWen Cao, Bo Zhang 0027, Yue Shi. 1-4 [doi]
• A Low-Power 10-bit 160-MSample/s DAC in 40-nm CMOS for Baseband Wireless TransmitterYifei Wang, Xiaofei Wang, Yuekang Guo, Ting Jin. 1-4 [doi]
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• Scalable Modeling for the CPW Gap Discontinuity at Frequency up to 150 GHzHao Sun, Jun Fu, Wenpu Cui, Tianling Ren, Linlin Liu, Wei Zhou, Quan Wang, Ao Guo. 1-3 [doi]
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• A 60 GHz single-to-differential LNA using slow-wave CPW and transformer coupling in 28 nm CMOSBenqing Guo, Haifeng Liu, Yao Wang, Jun Chen. 1-4 [doi]
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