Weiiie Xu, Yudi Zhao, Peng Huang 0004, Xiaoyan Liu, JinFeng Kang. 3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model. In 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019. pages 1-4, IEEE, 2019. [doi]
Abstract is missing.