Table of Contents

• Asynchronous Interface Specification, Analysis and SynthesisMichael Kishinevsky, Jordi Cortadella, Alex Kondratyev. 2-7 [doi]
• Automatic Synthesis of Interfaces Between Incompatible ProtocolsRoberto Passerone, James A. Rowson, Alberto L. Sangiovanni-Vincentelli. 8-13 [doi]
• Automated Composition of Hardware ComponentsJames Smith, Giovanni De Micheli. 14-19 [doi]
• Multilevel Integral Equation Methods for the Extraction of Substrate Coupling Parameters in Mixed-Signal IC sMike Chou, Jacob White. 20-25 [doi]
• Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for CharacterisationAlper Demir, Amit Mehrotra, Jaijeet S. Roychowdhury. 26-31 [doi]
• Efficient Analog Test Methodology Based on Adaptive AlgorithmsLuigi Carro, Marcelo Negreiros. 32-37 [doi]
• General AC Constraint Transformation for Analog ICsBogdan G. Arsintescu, Edoardo Charbon, Enrico Malavasi, Umakanta Choudhury, William H. Kao. 38-43 [doi]
• Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless TransceiverJacob Rael, Ahmadreza Rofougaran, Asad A. Abidi. 44-49 [doi]
• A Video Signal Processor for MIMD MultiprocessingJörg Hilgenstock, Klaus Herrmann, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch. 50-55 [doi]
• Realization of a Programmable Parallel DSP for High Performance Image Processing ApplicationsJens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch. 56-61 [doi]
• A Multiprocessor DSP System Using PADDI-2Roy A. Sutton, Vason P. Srini, Jan M. Rabaey. 62-65 [doi]
• Design and Implementation of the NUMAchine MultiprocessorA. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic. 66-69 [doi]
• Design and Specification of Embedded Systems in Java Using Successive, Formal RefinementJames Shin Young, Josh MacDonald, Michael Shilman, Abdallah Tabbara, Paul N. Hilfinger, A. Richard Newton. 70-75 [doi]
• Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data TransferJulio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt G. de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man. 76-81 [doi]
• Design Space Exploration Algorithm for Heterogeneous Multi-Processor Embedded System DesignIreneusz Karkowski, Henk Corporaal. 82-87 [doi]
• Modal Processes: Towards Enhanced Retargetability Through Control Composition of Distributed Embedded SystemsPai H. Chou, Gaetano Borriello. 88-93 [doi]
• Design Methodologies for Noise in Digital Integrated CircuitsKenneth L. Shepard. 94-99 [doi]
• Taming Noise in Deep Submicron Digital Integrated Circuits (Panel)N. S. Nagaraj, Kenneth L. Shepard, Takahide Inone. 100-101 [doi]
• ::::FACT::::: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral DescriptionsGanesh Lakshminarayana, Niraj K. Jha. 102-107 [doi]
• Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral DescriptionsGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha. 108-113 [doi]
• The DT-Model: High-Level Synthesis Using Data TransfersShantanu Tarafdar, Miriam Leeser. 114-117 [doi]
• Rate Optimal VLSI Design from Data Flow GraphMoonwook Oh, Soonhoi Ha. 118-121
• Planning for PerformanceRalph H. J. M. Otten, Robert K. Brayton. 122-127 [doi]
• A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement TogetherAmir H. Salek, Jinan Lou, Massoud Pedram. 128-134 [doi]
• Framework Encapsulations: A New Approach to CAD Tool InteroperabilityPeter R. Sutton, Stephen W. Director. 134-139 [doi]
• A Geographically Distributed Framework for Embedded System Design and ValidationKen Hines, Gaetano Borriello. 140-145 [doi]
• WELD - An Environment for Web-based Electronic DesignFrancis L. Chan, Mark D. Spiller, A. Richard Newton. 146-151 [doi]
• OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional VerificationFarzan Fallah, Srinivas Devadas, Kurt Keutzer. 152-157 [doi]
• Virtual Chip: Making Functional Models Work on Real Target SystemsNamseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung. 170-173 [doi]
• Hardware/Software Co-Design: The Next Embedded System Design Challenge (Panel)Peter Heller. 174-175 [doi]
• Power Optimization of Variable Voltage Core-Based SystemsInki Hong, Darko Kirovski, Gang Qu, Miodrag Potkonjak, Mani B. Srivastava. 176-181 [doi]
• Policy Optimization for Dynamic Power ManagementGiuseppe A. Paleologo, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli. 182-187 [doi]
• A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW SystemsYanbing Li, Jörg Henkel. 188-193 [doi]
• Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean SatisfiabilityPeixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi. 194-199 [doi]
• Fast Exact Minimization of BDDsRolf Drechsler, Nicole Drechsler, Wolfgang Günther. 200-205 [doi]
• Boolean Matching for Large LibrariesUwe Hinsberger, Reiner Kolla. 206-211 [doi]
• A Fast Hierarchical Algorithm for 3-D Capacitance ExtractionWeiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu. 212-217 [doi]
• Boundary Element Method Macromodels for 2-D Hierachical Capacitance ExtractionE. Aykut Dengi, Ronald A. Rohrer. 218-223 [doi]
• Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered Green s FunctionsJinsong Zhao, Wayne Wei-Ming Dai, Sharad Kapur, David E. Long. 224-229 [doi]
• Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS MicroprocessorNevine Nassif, Madhav P. Desai, Dale H. Hall. 230-235 [doi]
• A Top-Down Design Environment for Developing Pipelined DatapathsRobert M. McGraw, James H. Aylor, Robert H. Klenke. 236-241 [doi]
• Validation of an Architectural Level Power Analysis TechniqueRita Yu Chen, Robert Michael Owens, Mary Jane Irwin, Raminder Singh Bajwa. 242-245 [doi]
• Design Methodology of a 200MHz Superscalar Microprocessor: SH-4Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura. 246-249 [doi]
• How Much Analog Does a Designer Need to Know for Successful Mixed-Signal Design? (Panel)Stephan Ohr. 250 [doi]
• Hierarchical Algorithms for Assessing Probabilistic Constraints on System PerformanceGustavo de Veciana, Margarida F. Jacome, J.-H. Guo. 251-256 [doi]
• A Tool for Performance Estimation of Networked Embedded End-systemsAsawaree Kalavade, Pratyush Moghé. 257-262 [doi]
• Rate Derivation and Its Applications to Reactive, Real-Time Embedded SystemsAli Dasdan, Dinesh Ramanathan, Rajesh K. Gupta. 263-268 [doi]
• Generic Global Placement and FloorplanningHans Eisenmann, Frank M. Johannes. 269-274 [doi]
• Congestion Driven Quadratic PlacementPhiroze N. Parakh, Richard B. Brown, Karem A. Sakallah. 275-278 [doi]
• Potential-NRG: Placement with Incomplete DataMaogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh. 279-282 [doi]
• Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and ReplicationWen-Jong Fang, Allen C.-H. Wu. 283-286 [doi]
• Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground BounceJaewon Oh, Massoud Pedram. 287-290 [doi]
• Layout Extraction and Verification Methodology CMOS I/O CircuitsTong Li, Sung-Mo Kang. 291-296 [doi]
• A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D InterconnectsNuno Alexandre Marques, Mattan Kamon, Jacob White, Luis Miguel Silveira. 297-302 [doi]
• Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing AnalysisByron Krauter, Sharad Mehrotra. 303-308 [doi]
• A Methodology for Guided Behavioral-Level OptimizationLisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey. 309-314 [doi]
• A Programming Environment for the Design of Complex High Speed ASICsPatrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens. 315-320 [doi]
• Media Architecture: General Purpose vs. Multiple Application-Specific Programmable ProcessorChunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith. 321-326 [doi]
• User Experience with High Level Formal Verification (Panel)Randal E. Bryant, Gerry Musgrave. 327 [doi]
• What s Between Simulation and Formal Verification? (Extended Abstract)David L. Dill. 328-329 [doi]
• Optimal FPGA Mapping and Retiming with Efficient Initial State ComputationJason Cong, Chang Wu. 330-335 [doi]
• M32: A Constructive multilevel Logic Synthesis SystemVictor N. Kravets, Karem A. Sakallah. 336-341 [doi]
• Efficient Boolean Division and SubstitutionShih-Chieh Chang, David Ihsin Cheng. 342-347 [doi]
• Delay-Optimal Technology Mapping by DAG CoveringYuji Kukimoto, Robert K. Brayton, Prashant Sawkar. 348-351 [doi]
• A Fast Fanout Optimization Algorithm for Near-Continuous Buffer LibrariesDavid S. Kung. 352-355 [doi]
• Performance Driven Multi-Layer General Area Routing for PCB/MCM DesignsJason Cong, Patrick H. Madden. 356-361 [doi]
• Buffer Insertion for Noise and Delay OptimizationCharles J. Alpert, Anirudh Devgan, Stephen T. Quay. 362-367 [doi]
• Table-Lookup Methods for Improved Performance-Driven RoutingJohn Lillis, Premal Buch. 368-373 [doi]
• Global Routing with Crosstalk ConstraintsHai Zhou, D. F. Wong. 374-377 [doi]
• Timing and Crosstalk Driven Area RoutingHsiao-Ping Tseng, Louis Scheffer, Carl Sechen. 378-381 [doi]
• Process Multi-Circuit OptimizationArun N. Lokanathan, Jay B. Brockman. 382-387 [doi]
• Migration: A New Technique to Improve Synthesized Designs Through Incremental CustomizationRajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw. 388-391 [doi]
• A Practical Repeater Insertion Method in High Speed VLSI CircuitsJulian Culetu, Chaim Amir, John MacDonald. 392-395 [doi]
• Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts?Paolo Ienne, Alexander Grießing. 396-401 [doi]
• A Statistical Performance Simulation Methodology for VLSI CircuitsMichael Orshansky, James C. Chen, Chenming Hu. 402-407 [doi]
• RF IC Design ChallengesBehzad Razavi. 408-413 [doi]
• Tools and Methodology for RF IC DesignAl Dunlop, Alper Demir, Peter Feldmann, Sharad Kapur, David E. Long, Robert C. Melville, Jaijeet S. Roychowdhury. 414-420 [doi]
• Efficient Coloring of a Large Spectrum of GraphsDarko Kirovski, Miodrag Potkonjak. 427-432 [doi]
• Arithmetic Optimization Using Carry-Save-AddersTaewhan Kim, William Jao, Steven W. K. Tjiang. 433-438 [doi]
• Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral DescriptionsGanesh Lakshminarayana, Niraj K. Jha. 439-444 [doi]
• Approximation and Decomposition of Binary Decision DiagramsKavita Ravi, Kenneth L. McMillan, Thomas R. Shiple, Fabio Somenzi. 445-450 [doi]
• Approximate Reachability with BDDs Using Overlapping ProjectionsShankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark Horowitz. 451-456 [doi]
• Incremental CTL Model Checking Using BDD SubsettingAbelardo Pardo, Gary D. Hachtel. 457-462 [doi]
• ::::ftd::::: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect ModelsYing Liu, Lawrence T. Pileggi, Andrzej J. Strojwas. 469-472 [doi]
• Extending Moment Computation to 2-Port Circuit RepresentationsFang-Jou Liu, Chung-Kuan Cheng. 473-476 [doi]
• Adjoint Transient Sensitivity Computation in Piecewise Linear SimulationTuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov. 477-482 [doi]
• Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling TechniquesKimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda. 483-488 [doi]
• Design and Optimization of Low Voltage High Performance Dual Threshold CMOS CircuitsLiqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De. 489-494 [doi]
• MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge PatternsJames Kao, Siva Narendra, Anantha Chandrakasan. 495-500 [doi]
• Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel)A. Richard Newton. 501 [doi]
• Software Synthesis of Process-Based Concurrent ProgramsBill Lin. 502-505 [doi]
• Don t Care-Based BDD Minimization for Embedded SoftwareYoupyo Hong, Peter A. Beerel, Luciano Lavagno, Ellen Sentovich. 506-509 [doi]
• Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code GeneratorSilvina Hanono, Srinivas Devadas. 510-515 [doi]
• Code Compression for Embedded SystemsHaris Lekatsas, Wayne Wolf. 516-521 [doi]
• A Decision Procedure for Bit-Vector ArithmeticClark W. Barrett, David L. Dill, Jeremy R. Levitt. 522-527 [doi]
• Functional Vector Generation for HDL Models Using Linear Programming and 3-SatisfiabilityFarzan Fallah, Srinivas Devadas, Kurt Keutzer. 528-533 [doi]
• Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory EvaluationLi-C. Wang, Magdy S. Abadir, Nari Krishnamurthy. 534-537 [doi]
• Combining Theorem Proving and Trajectory Evaluation in an Industrial EnvironmentMark Aagaard, Robert B. Jones, Carl-Johan H. Seger. 538-541 [doi]
• A Fast and Low Cost Testing Technique for Core-Based System-on-ChipIndradeep Ghosh, Sujit Dey, Niraj K. Jha. 542-547 [doi]
• Introducing Redundant Computations in a Behavior for Reducing BIST ResourcesIshwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer. 548-553 [doi]
• A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability AnalysisIndradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik. 554-559 [doi]
• Figures of Merit to Characterize the Importance of On-Chip InductanceYehea I. Ismail, Eby G. Friedman, José Luis Neves. 560-565 [doi]
• Layout Techniques for Minimizing On-Chip Interconnect Self InductanceYehia Massoud, Steve S. Majors, Tareq Bustami, Jacob White. 566-571 [doi]
• A Practical Approach to Static Signal Electromigration AnalysisN. S. Nagaraj, Frank Cano, Haldun Haznedar, Duane Young. 572-577 [doi]
• Design Productivity: How To Measure It, How To Improve It (Panel)Carlos Dangelo. 578-579 [doi]
• Hierarchical Functional Timing AnalysisYuji Kukimoto, Robert K. Brayton. 580-585 [doi]
• Making Complex Timing Relationships Readable: Presburger Formula Simplicication Using Don t CaresTod Amon, Gaetano Borriello, Jiwen Liu. 586-590 [doi]
• Delay Estimation VLSI Circuits from a High-Level ViewMahadevamurty Nemani, Farid N. Najm. 591-594 [doi]
• TETA: Transistor-Level Engine for Timing AnalysisFlorentin Dartu, Lawrence T. Pileggi. 595-598 [doi]
• Validation with Guided Search of the State SpaceC. Han Yang, David L. Dill. 599-604 [doi]
• Efficient State Classification of Finite State Markov ChainsAiguo Xie, Peter A. Beerel. 605-610 [doi]
• An Implicit Algorithm for Finding Steady States and its Application to FSM VerificationGagan Hasteer, Anmol Mathur, Prithviraj Banerjee. 611-614 [doi]
• Hybrid Verification Using Saturated SimulationAdnan Aziz, James H. Kukula, Thomas R. Shiple. 615-618 [doi]
• Fast State VerificationDechang Sun, Bapiraju Vinnakota, Wanli Jiang. 619-624 [doi]
• A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG PerformanceAiman H. El-Maleh, Mark Kassab, Janusz Rajski. 625-631 [doi]
• Fault-Simulation Based Design Error Diagnosis for Sequential CircuitsShi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu. 632-637 [doi]
• Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 MicroprocessorScott A. Taylor, Michael Quinn, Darren Brown, Nathan Dohm, Scot Hildebrandt, James Huggins, Carl Ramey. 638-643 [doi]
• Design Reliability - Estimation through Statistical Analysis of Bug Discovery DataYossi Malka, Avi Ziv. 644-649 [doi]
• Functional Verification of Large ASICsAdrian Evans, Allan Silburt, Gary Vrckovnik, Thane Brown, Mario Dufresne, Geoffrey Hall, Tung Ho, Ying Liu. 650-655 [doi]
• Digital System Simulation: Methodologies and ExamplesKunle Olukotun, Mark Heinrich, David Ofelt. 658-663 [doi]
• Hybrid Techniques for Fast Functional SimulationYufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz. 664-667 [doi]
• Parallel Algorithms for Power EstimationVictor Kim, Prithviraj Banerjee. 672-677 [doi]
• A Power Macromodeling Technique Based on Power SensitivityZhanping Chen, Kaushik Roy. 678-683 [doi]
• Maximum Power Estimation Using the Limiting Distributions of Extreme Order StatisticsQinru Qiu, Qing Wu, Massoud Pedram. 684-689 [doi]
• An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic CircuitsByunggyu Kwak, Eun Sei Park. 690-693 [doi]
• Using Complementation and Resequencing to Minimize TransitionsRajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira. 694-697 [doi]
• Technology Mapping for Large Complex PLDsJason Helge Anderson, Stephen Dean Brown. 698-703 [doi]
• Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTsJason Cong, Songjie Xu. 704-707 [doi]
• Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTsMadhukar R. Korupolu, K. K. Lee, D. F. Wong. 708-711 [doi]
• Compatible Class Encoding in Hyper-Function Decomposition for FPGA SynthesisJie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang. 712-717 [doi]
• In-Place Power Optimization for LUT-Based FPGAsBalakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi. 718-721 [doi]
• A Re-engineering Approach to Low Power FPGA Design Using SPFDJan-Min Hwang, Feng-Yi Chiang, TingTing Hwang. 722-725 [doi]
• Power Considerations in the Design of the Alpha 21264 MicroprocessorMichael K. Gowan, Larry L. Biro, Daniel B. Jackson. 726-731 [doi]
• Reducing Power in High-Performance MicroprocessorsVivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav Mehta, Rakesh Patel, Franklin Baez. 732-737 [doi]
• Design and Analysis of Power Distribution Networks in PowerPC MicroprocessorsAbhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden. 738-743 [doi]
• Full-Chip Verification Methods for DSM Power Distribution SystemsGregory Steele, David Overhauser, Steffen Rochel, Syed Zakir Hussain. 744-749 [doi]
• System Chip Test Challenges, Are There Solutions Today? (Panel)Prab Varma. 750-751 [doi]
• System-Chip Test Strategies (Tutorial)Yervant Zorian. 752-757 [doi]
• Computational Kernels and their Application to Sequential Power OptimizationLuca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino. 764-769 [doi]
• Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level DescriptionsAndrew Seawright, Wolfgang Meyer. 770-775 [doi]
• Watermarking Techniques for Intellectual Property ProtectionAndrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe. 776-781 [doi]
• Robust IP Watermarking Methodologies for Physical DesignAndrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe. 782-787 [doi]
• Data Security for Web-based CADScott Hauck, Stephen Knol. 788-793 [doi]
• Design of a SPDIF Receiver Using Protocol CompilerUlrich Holtmann, Peter Blinzer. 794-799 [doi]
• MetaCore: An Application Specific DSP Development SystemJin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung. 800-803 [doi]
• A Case Study in Embedded System Design: An Engine Control UnitTullio Cuatto, Claudio Passerone, Luciano Lavagno, Attila Jurecska, Antonino Damiano, Claudio Sansoè, Alberto L. Sangiovanni-Vincentelli. 804-807 [doi]
• System-level exploration with SpecSynDaniel Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong. 812-817 [doi]