Paul Six - researchr alias

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Viewing Publication 1 - 13 from 13

1998

1995

Timing optimization by bit-level arithmetic transformationsLuc Rijnders, Zohair Sahraoui, Paul Six, Hugo De Man. eurodac 1995: 48-53 [doi]

Search space reduction through clustering in test generationZohair Sahraoui, Paul Six, Ivo Bolsens, Hugo De Man. eurodac 1995: 242-247 [doi]

1992

Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building BlocksEvagelos Katsadas, Zohair Sahraoui, M. Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man. ifip10-2 1993: 167-181

Flag/Condition Handling and Branch Assignment for Large Microcoded ControllersAugusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man. ifip10-2 1993: 61-71

1991

DARSI: RC data reduction [VLSI simulation]Paul Vanoostende, Paul Six, Hugo De Man. tcad, 10(4):493-500, 1991. [doi]

1990

A Data Path Layout Assembler for High Performance DSP CircuitsH. Cai, Stefaan Note, Paul Six, Hugo De Man. dac 1990: 306-311 [doi]

CGE: automatic generation of controllers in the CATHEDRAL-II silicon compilerJ. Zegers, Paul Six, Jan M. Rabaey, Hugo De Man. eurodac 1990: 617-621 [doi]

1989

REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular StructuresI. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man. dac 1989: 694-697 [doi]

REDUSA: module generation by automatic elimination of superfluous blocks in regular structuresI. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man. tcad, 8(9):989-998, 1989. [doi]

1986

Cathedral-II: A Silicon Compiler for Digital Signal ProcessingHugo De Man, Jan M. Rabaey, Paul Six, Luc J. M. Claesen. dt, 3(6):13-25, 1986. [doi]

An intelligent module generator environmentPaul Six, Luc J. M. Claesen, Jan M. Rabaey, Hugo De Man. dac 1986: 730-735 [doi]

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