Yuji Kukimoto - researchr alias

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Viewing Publication 1 - 18 from 18

2024

Calibration-Based Differentiable Timing Optimization in Non-linear Global PlacementWuxi Li, Yuji Kukimoto, Grégory Servel, Ismail Bustany, Mehrdad E. Dehkordi. ispd 2024: 31-39 [doi]

2002

On convergence of switching windows computation in presence of crosstalk noisePinhong Chen, Yuji Kukimoto, Chin-Chi Teng, Kurt Keutzer. ispd 2002: 84-89 [doi]

Refining switching window by time slots for crosstalk noise calculationPinhong Chen, Yuji Kukimoto, Kurt Keutzer. iccad 2002: 583-586 [doi]

1999

Timing-safe false path removal for combinational modulesYuji Kukimoto, Robert K. Brayton. iccad 1999: 544-550 [doi]

1998

Combinational Verification based on High-Level Functional SpecificationsEvguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton. date 1998: 803 [doi]

Delay-Optimal Technology Mapping by DAG CoveringYuji Kukimoto, Robert K. Brayton, Prashant Sawkar. dac 1998: 348-351 [doi]

Hierarchical Functional Timing AnalysisYuji Kukimoto, Robert K. Brayton. dac 1998: 580-585 [doi]

1997

Exact Required Time Analysis via False Path DetectionYuji Kukimoto, Robert K. Brayton. dac 1997: 220-225 [doi]

Approximate timing analysis of combinational circuits under the XBD0 modelYuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton. iccad 1997: 176-181 [doi]

1996

1994

A redesign technique for combinational circuits based on gate reconnectionsYuji Kukimoto, Masahiro Fujita, Robert K. Brayton. iccad 1994: 632-637 [doi]

1992

Patching Method for Lookup-Table Type FPLsMasahiro Fujita, Yuji Kukimoto. fpga 1993: 61-70

Rectification method for lookup-table type FPGA sYuji Kukimoto, Masahiro Fujita. iccad 1992: 54-61 [doi]

1991

Application of Boolean Unification to Combinational Logic SynthesisMasahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen. iccad 1991: 510-513

1990

Practical design assistance at register transfer level using a data path verifierHiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka. iccd 1990: 99-102 [doi]

A Data Path Verifier for Register Transfer Level Using Temporal Logic Language TokioHiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka. dimacs 1991: 493-504

A Data Path Verifier for Register Transfer Level Using Temporal Logic Language TokioHiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka. cav 1991: 76-85

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