Table of Contents

• Engineering the Future of IC Design with AIRuchir Puri. 1 [doi]
• MedPart: A Multi-Level Evolutionary Differentiable Hypergraph PartitionerRongjian Liang, Anthony Agnesina, Haoxing Ren. 3-11 [doi]
• FuILT: Full Chip ILT System With Boundary HealingShuo Yin, Wenqian Zhao, Li Xie, Hong Chen, Yuzhe Ma, Tsung-Yi Ho, Bei Yu 0001. 13-20 [doi]
• Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-FlopsYen-Yu Chen, Hao-Yu Wu, Iris Hui-Ru Jiang, Cheng-Hong Tsai, Chien-Cheng Wu. 21-29 [doi]
• Calibration-Based Differentiable Timing Optimization in Non-linear Global PlacementWuxi Li, Yuji Kukimoto, Grégory Servel, Ismail Bustany, Mehrdad E. Dehkordi. 31-39 [doi]
• Novel Airgap Insertion and Layer Reassignment for Timing Optimization Guided by Slack DependencyWei Chen Tai, Min-Hsien Chung, Iris Hui-Ru Jiang. 41-49 [doi]
• Parallel and Heterogeneous Timing Analysis: Partition, Algorithm, and SystemTsung-Wei Huang, Boyang Zhang, Dian-Lun Lin, Cheng-Hsiang Chiu. 51-59 [doi]
• Introduction to the Panel on EDA Challenges at Advanced Technology NodesTung-Chieh Chen. 61 [doi]
• Panel Statement: EDA Needs at Advanced Technology NodesAndrew B. Kahng. 63 [doi]
• Large Language Models for EDA: Future or Mirage?Zhuolun He, Bei Yu 0001. 65-66 [doi]
• PANEL: EDA Challenges at Advanced Technology Nodes AEugene Liu. 67 [doi]
• PANEL: EDA Challenges at Advanced Technology Nodes BGuang-Wan Liao. 69 [doi]
• Challenges in Floorplanning and Macro Placement for Modern SoCsI-Lun Tseng. 71-72 [doi]
• PANEL: EDA Challenges at Advanced Technology Nodes CKeh-Jeng Chang. 73 [doi]
• Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICsSiting Liu 0002, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu 0001, Martin D. F. Wong. 75-82 [doi]
• Unified 3D-IC Multi-Chiplet System Design SolutionWang-Tyng Lay. 83 [doi]
• Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction EffectsJun-Ho Choy, Stéphane Moreau, Catherine Brunet-Manquat, Valeriy Sukharev, Armen Kteyan. 85-90 [doi]
• Challenges for Automating PCB LayoutWen-Hao Liu, Anthony Agnesina, Haoxing Mark Ren. 91-92 [doi]
• FastTuner: Transferable Physical Design Parameter Optimization using Fast Reinforcement LearningHao-Hsiang Hsiao, Yi-Chen Lu, Pruek Vanna-Iampikul, Sung Kyu Lim. 93-101 [doi]
• Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction ModelSuwan Kim, Hyunbum Park, Kyeonghyeon Baek, Kyumyung Choi, Taewhan Kim. 103-111 [doi]
• AI for EDA/Physical Design: Driving the AI Revolution: The Crucial Role of 3D-ICErick Chao. 113 [doi]
• DSO.ai - A Distributed System to Optimize Physical Design FlowsPiyush Verma. 115-116 [doi]
• Solvers, Engines, Tools and Flows: The Next Wave for AI/ML in Physical DesignAndrew B. Kahng. 117-124 [doi]
• Physical Design Challenges in Modern Heterogeneous IntegrationYao-Wen Chang. 125-134 [doi]
• Fundamental Differences Between Analog and Digital Design Problems - An IntroductionJürgen Scheible. 135-136 [doi]
• Layout Verification Using Open-Source SoftwareAndreas Krinke, Robert Fischbach, Jens Lienig. 137-142 [doi]
• Reinforcement Learning or Simulated Annealing for Analog Placement? A Study based on Bounded-Sliceline GridsMark Po-Hung Lin, Chou-Chen Lee, Yi-Chao Hsieh. 143-150 [doi]
• Practical Mixed-Cell-Height Legalization Considering Vertical Cell Abutment ConstraintTeng-Ping Huang, Shao-Yun Fang. 151-159 [doi]
• Multi-Electrostatics Based Placement for Non-Integer Multiple-Height CellsYu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu 0004, Yibo Lin, Bei Yu 0001. 161-168 [doi]
• IncreMacro: Incremental Macro Placement RefinementYuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu. 169-176 [doi]
• Timing-Driven Analytical Placement According to Expected Cell Distribution RangeJai-Ming Lin, You-Yu Chang, Wei-Lun Huang. 177-184 [doi]
• Routability Booster " Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL ResourcesBing-Xun Song, Ting Xin Lin, Yih-Lang Li. 185-193 [doi]
• Novel Transformer Model Based Clustering Method for Standard Cell Design AutomationChia-Tung Ho, Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li, Haoxing Ren. 195-203 [doi]
• Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability OptimizationChien Pang Lu, Iris Hui-Ru Jiang, Chung-Ching Peng, Mohd Mawardi Mohd Razha, Alessandro Uber. 205-212 [doi]
• Introduction of 3D IC Thermal Analysis FlowAlex Hung. 213 [doi]
• 3Dblox: Unleash the Ultimate 3DIC Design ProductivityJim Chang. 215 [doi]
• Enabling System Design in 3D Integration: Technologies and MethodologiesHung-Ming Chen. 217 [doi]
• Scheduling and Physical DesignJason Cong. 219-225 [doi]
• Accelerating Physical Design from 1 to NEvangeline F. Y. Young. 227 [doi]
• Pioneering Contributions of Professor Martin D. F. Wong to Automatic Floorplan DesignTing-Chi Wang. 229 [doi]
• ISPD 2024 Lifetime Achievement Award BioMartin D. F. Wong. 231 [doi]
• Computing Architecture for Large-Language Models (LLMs) and Large Multimodal Models (LMMs)Bor-Sung Liang. 233-234 [doi]
• SMT-Based Layout Synthesis Approaches for Quantum CircuitsZi-Hao Guo, Ting-Chi Wang. 235-243 [doi]
• Satisfiability Modulo Theories-Based Qubit Mapping for Trapped-Ion Quantum Computing SystemsWei-Hsiang Tseng, Yao-Wen Chang, Jie-Hong Roland Jiang. 245-253 [doi]
• Optimization for Buffer and Splitter Insertion in AQFP Circuits with Local and Group MovementBing-Huan Wu, Wai-Kei Mak. 255-262 [doi]
• Design Automation Challenges for Automotive SystemsChung-Wei Lin. 263 [doi]
• Physical Design Challenges for Automotive ASICsGoeran Jerke. 265 [doi]
• Solving the Physical Challenges for the Next Generation of Safety Critical & High Reliability SystemsRob Knoth. 267 [doi]
• GPU/ML-Enhanced Large Scale Global Routing ContestRongjian Liang, Anthony Agnesina, Wen-Hao Liu, Haoxing Ren. 269-274 [doi]