Abstract is missing.
- Overview of Complex Array-Based PLDsGünter Biehl. 1-10
- Technologies and Utilization fo Field Programmable Gate ArraysJouni Isoaho, Arto Nummela, Hannu Tenhunen. 11-25
- Some Considerations on Field-Programmable Gate Arrays and Their Impact on System DesignAlberto L. Sangiovanni-Vincentelli. 26-34
- SRAM-Based FPLs Ease System VerificationBradly K. Fawcett. 35-43
- MONTAGNE: An FPL for Synchronous and Asynchronous CircuitsScott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling. 44-51
- ORCA: A New Architecture for High-Performance FPLsDwight D. Hill, Barry K. Britton, William Oswald, Nam Sung Woo, Satwant Singh, Che-Tsung Chen, Bob Krambeck. 52-60
- Patching Method for Lookup-Table Type FPLsMasahiro Fujita, Yuji Kukimoto. 61-70
- Automatic One-Hot Re-Encoding for FPLsDave Allen. 71-77
- Minimization of Permuted Reed-Muller Trees for Cellular LogicLi-Fei Wu, Marek A. Perkowski. 78-87
- Self-Organizing Kohonen Maps for FPL PlacementDavid C. Blight, Robert D. McLeod. 88-95
- High Level Synthesis in an FPL-Based Computer Aided Prototyping EnvironmentPeter Poechmueller, Hans-Jürgen Herpel, Manfred Glesner, Fang Longsen. 96-105
- New Application of FPLs to Programmable Digital Communication CirucitsNaohisa Ohta, Kazuhisa Yamada, Akihiro Tsutsui, Hiroshi Nakada. 106-111
- FPL Based Logic Synthesis of Squarers Using VHDLGeorg J. Kempa, Peter Jung. 112-123
- Optimized Fuzzy Controller Architecture for Field Programmable Gate ArraysHartmut Surmann, Ansgar Ungering, Karl Goser. 124-133
- A Real-Time Kernel - Rapid Prototyping with VHDL and FPLsLennart Lindh, Klaus D. Müller-Glaser, Hans Rauch, Frank Stanischewski. 134-145
- JAPROC - An 8 bit Micro Controller Design and Its Test EnvironmentHerbert Grünbacher, Alexander Jaud. 146-151
- Chameleon: A Workstation of a Different ColourBeat Heeb, Cuno Pfister. 152-161
- A Highly Parallel FPL-Based Machine and Its Formal VerificationPaul Shaw, George J. Milne. 162-173
- FPL Based Self-Test with Deterministic Test PatternsArno Kunzmann. 174-182
- FPL Implementation of Systolic Sequence AlignmentDzung T. Hoang, Daniel P. Lopresti. 183-191
- Using FPLs to Prototoype a Self-Timed ComputerErik Brunvand. 192-198
- Using FPLs to Implement a Reconfigurable Highly Parallel ComputerArne Linde, Tomas Nordström, Mikael Taveniku. 199-210
- Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design MethodsAndreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt. 211-217